Digital phase-locked loop supply voltage control

Patent metadata

Field	Value
Publication number	US-9866225-B2
Application number	US-201615161511-A
Country	US
Kind code	B2
Filing date	May 23, 2016
Priority date	Sep 18, 2014
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.

First claim

What is claimed is:

1. An apparatus comprising:
a voltage generator to generate a voltage;
a circuit to generate output signal having a frequency based on a value of a digital information in a first control loop; and
a monitor in a second control loop to monitor the value of the digital information and to decrease a value of the voltage if the value of the digital information is less than a value of a lower limit of the value range, and to increase the value of the voltage if the value of the digital information is greater than a value of an upper limit of the value range, wherein the second control loop is arranged to operate at a frequency less than a frequency of the first control loop.

2. The apparatus of claim 1 , wherein the voltage generator includes a bandgap reference generator to generate a reference voltage and the voltage is generated based on the reference voltage.

3. The apparatus of claim 2 , wherein the bandgap reference generator includes an adjustable resistor having a resistance value based on the value of the digital information, and the value of the reference voltage is based at least in part on the resistance value.

4. An apparatus comprising:
a voltage generator to generate a voltage;
a circuit to generate output signal having a frequency based on a value of a digital information in a first control loop; and
a monitor in a second control loop to monitor the value of the digital information and to adjust the value of the voltage based on the value of the digital information, wherein the voltage generator includes a bandgap reference generator to generate a reference voltage, and a filter to generate a filtered voltage based on the reference voltage, and the voltage is generated based on the filtered voltage, wherein the second control loop is arranged to operate at a frequency less than a frequency of the first control loop.

5. The apparatus of claim 1 , wherein the voltage generating unit includes an adjustable resistor divider to generate the voltage at a node of the voltage divider.

6. The apparatus of claim 5 , wherein the adjustable resistor divider includes an adjustable resistor having a resistance value based on the value of the digital information.

7. An apparatus comprising:
a voltage generator to generate a voltage;
a circuit to generate output signal having a frequency based on a value of a digital information in a first control loop; and
a monitor in a second control loop to monitor the value of the digital information and to adjust the value of the voltage based on the value of the digital information, wherein the monitor is to adjust the value of the supply voltage if the value of the digital information is outside a value range, and the value range of the digital information has lower limit greater than a minimum value of the digital information and an upper limit less than a maximum value of the digital information, wherein the second control loop is arranged to operate at a frequency less than a frequency of the first control loop.

8. The apparatus of claim 7 , wherein the value range of the digital information is associated with a portion of a frequency range of the output signal.

9. An apparatus comprising:
a digitally controlled oscillator to receive a supply voltage and to generate an output signal;
a first control loop to generate a digital information to control a frequency of the digitally controlled oscillator; and
a second control loop to decrease the value of the supply voltage if the value of the digital information is less than a value of a lower limit of the value range, and to increase the value of the supply voltage if the value of the digital information is greater than a value of an upper limit of the value range, wherein the second control loop is arranged to operate at a frequency less than a frequency of the first control loop.

10. The apparatus of claim 9 , wherein the digitally controlled oscillator includes inverting stages arranged in a ring arrangement.

11. The apparatus of claim 9 , wherein the digitally controlled oscillator includes capacitive loads coupled to the inverting stages, each of the capacitor loads having a capacitance value based on the value of the digital information.

12. The apparatus of claim 9 , wherein the first control loop includes a time-to-digital converter to generate a digital representation of the output signal.

13. The apparatus of claim 12 , wherein the first control loop includes a phase frequency detector to compare the digital representation of the output signal with a digital representation of a reference signal and generate a result, and a digital filter to generate the digital information based on the result.

14. The apparatus of claim 9 , wherein the second control loop includes a bandgap reference generator to generate a bandgap reference voltage, wherein the supply voltage is generated based on the bandgap reference voltage.

15. The apparatus of claim 9 , wherein the second control loop includes:
an adjustable resistor divider to generate a voltage;
an RC filter to receive the voltage and generate a filtered voltage; and
a driver to receive the filtered voltage and provide the supply voltage.

16. A system comprising:
memory device; and
a processor coupled to the memory device, the processor including:
a voltage generator to generate a supply voltage;
a circuit to generate output signal having a frequency based on a value of a digital information in a first control loop; and
a monitor in a second control loop to monitor the value of the digital information and to decrease a value of the supply voltage if the value of the digital information is less than a value of a lower limit of the value range, and to increase the value of the supply voltage if the value of the digital information is greater than a value of an upper limit of the value range, wherein the second control loop is arranged to operate at a frequency less than a frequency of the first control loop.

17. The system of claim 16 , wherein the memory device and the processor are located on a same die.

18. The system of claim 16 , wherein the control loop includes a bandgap reference generator to generate a bandgap reference voltage, and a driver to provide the supply voltage based on the bandgap reference voltage to the digitally controlled oscillator.

Assignees

• Intel Corp

Inventors

• Familia Noam
• Saksonov Avigdor
• Fayneh Eyal
• Shor Joseph

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0991 Primary

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title