Clock recovery circuit, related clock and data recovery circuit, receiver, integrated circuit and method

Patent metadata

Field	Value
Publication number	US-9866223-B2
Application number	US-201615190020-A
Country	US
Kind code	B2
Filing date	Jun 22, 2016
Priority date	Dec 7, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A clock recovery circuit includes an oscillator to generate a clock signal. The oscillator varies a frequency of the clock signal as a function of a control signal. The clock recovery circuit has a phase tracking control loop to determine the phase error between the reference signal and the clock signal, and vary the control signal as a function of the phase error. The phase tracking control loop has a linear region for phase errors in the range between −π and +π, thereby creating a cycle slippage event when the phase error exceed said range. The clock recovery circuit includes a cycle-slippage detector which determines whether the phase error reaches or approaches +π or −π. In case the phase error reaches or approaches +π or −π, the cycle-slippage detector acts on the control signal in an effort to avoid that said phase tracking control loop leaves said linear region.

First claim

The invention claimed is:

1. A device, comprising:
an oscillator, which, in operation, generates a clock signal having a frequency based on a control signal; and
oscillator control circuitry, which, in operation:
determines a phase error between a reference signal and the clock signal; detects cycle-slippage based on whether the phase error is within a threshold phase-error range; and
generates the control signal based on the determined phase error and on whether cycle-slippage has been detected, wherein said oscillator control circuitry, in operation:
generates at least one positive charge pulse when said phase error approaches or reaches +π; and
generates at least one negative charge pulse when said phase error approaches or reaches −π.

2. The device of claim 1 wherein the reference signal comprises at least one of a data signal and a reference clock signal.

3. The device of claim 1 wherein, the threshold phase-error range extends between one of:
+π and −π; and
+π−delta and −π+delta, where delta is a threshold value.

4. The device of claim 1 wherein said oscillator control circuitry comprises cycle-slippage detection circuitry, which, in operation, monitors said reference signal and said clock signal to determine whether said phase error is at least one 2π cycle.

5. The device of claim 1 wherein said oscillator control circuitry includes a cycle slip balancer control loop having a frequency detector, which, in operation, detects whether the phase error is within the threshold range by determining at least one of:
whether an edge of said clock signal overruns a corresponding edge of said reference signal; and
whether an edge of said reference signal overruns a corresponding edge of said clock signal.

6. The device of claim 5 wherein said cycle slip balancer and a phase tracking loop of the oscillator control circuitry have substantially a same response time.

7. The device of claim 5 wherein said oscillator control circuitry comprises:
a loop filter configured to generate said control signal of said oscillator; and
a first charge pump configured to provide charge pulses to said loop filter as a function of at least one charge-pump control signal, wherein said frequency detector is configured to generate said at least one charge-pump control signal.

8. The device of claim 1 wherein said oscillator control circuitry comprises:
a loop filter configured to generate said control signal of said oscillator;
a charge pump configured to provide charge pulses to said loop filter as a function of at least one charge-pump control signal; and
a phase detector configured to determine said phase error between said clock signal and said reference signal.

9. The device of claim 1 , wherein said oscillator is a voltage controlled oscillator.

10. A device, comprising:
an oscillator, which, in operation, generates a clock signal having a frequency based on a control signal;
oscillator control circuitry, which, in operation:
determines a phase error between a reference signal and the clock signal;
detects cycle-slippage based on whether the phase error is within a threshold phase-error range; and
generates the control signal based on the determined phase error and on whether cycle-slippage has been detected; and

a frequency tracking control loop, which, in operation:
determines a frequency difference between said clock signal and said reference signal; and
modifies said control signal as a function of said frequency difference, wherein said frequency tracking control loop has a response time greater than a response time of a phase tracking loop of the oscillator control circuitry.

11. The device of claim 10 wherein said oscillator control circuitry, in operation:
generates at least one positive charge pulse when said phase error approaches or reaches +π; and
generates at least one negative charge pulse when said phase error approaches or reaches −π.

12. The device of claim 10 wherein, in operation:
said frequency tracking control loop is enabled during start-up or loss of synchronization to perform a coarse regulation of said control signal; and
a cyclic slip balancer of the oscillator control circuitry and the phase tracking control loop are enabled during data reception to perform a fine regulation of said control signal.

13. A system, comprising:
a clock recovery circuit, including:
an oscillator, which, in operation, generates a clock signal having a frequency based on a control signal;
a phase-tracking loop, which, in operation:
determines a phase error between a data signal and the clock signal; and
generates the control signal based on the determined phase error; and

cycle-slippage detection circuitry, which, in operation:
detects cycle-slippage based on whether the phase error is within a threshold phase-error range; and
modifies the control signal in response to detection of cycle slippage; and

data-recovery circuitry, which, in operation recovers data transmitted via said data signal as a function of said clock signal and said data signal, wherein said cycle-slippage detection circuitry, in operation:
generates at least one positive charge pulse when said phase error approaches or reaches +π; and
generates at least one negative charge pulse when said phase error approaches or reaches −π.

14. The system of claim 13 wherein the data-recovery circuitry comprises at least one of:
a delay-locked loop; and
one or more flip-flops coupled in cascade.

15. The system of claim 13 , comprising:
an optical receiver.

16. The system of claim 15 wherein the optical receiver is compatible with a Synchronous Optical Network.

17. The system of claim 13 wherein the threshold phase-error range extends between one of:
+π and −π; and
+π−delta and −π+delta, where delta is a threshold value.

18. The system of claim 13 , comprising:
an integrated circuit including at least one of the clock recovery circuit and the data-recovery circuitry.

19. The system of claim 13 wherein said cycle-slippage detection circuitry includes a cycle slip balancer control loop having a frequency detector, which, in operation, detects whether the phase error is within the threshold range by determining at least one of:
whether an edge of said clock signal overruns a corresponding edge of said reference signal; and
whether an edge of said reference signal overruns a corresponding edge of said clock signal.

20. A method, comprising:
generating a clock signal having a frequency based on a control signal;
determining a phase error between a reference signal and the clock signal;
detecting cycle-slippage based on whether the phase error is within a threshold phase-error range; and
generating the control signal based on the determined phase error and on whether cycle-slippage has been detected, wherein the method includes:
generating at least one positive charge pulse when said phase error approaches or reaches +π; and
generating at least one negative charge pulse n said phase error approaches or reaches −π.

21. The method of claim 20 wherein the reference signal comprises at least one of a data signal and a reference clock signal.

22. The method of claim 20 wherein the threshold phase-error range extends between one of:
+π and −π; and
+π−delta and −π+delta, where delta is a threshold value.

23. The method of claim 20 , comprising:
monitoring said reference signal and said clock signal to determine wheth

Assignees

• St Microelectronics Srl

Inventors

• Guinea Trigo Jesus Alejandro

Classifications

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H04L7/0079

  Receiver details · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/14

  for assuring constant frequency when supply or correction voltages fail · CPC title