Systems and methods for operating radio transceivers

Patent metadata

Field	Value
Publication number	US-2016191231-A1
Application number	US-201414582186-A
Country	US
Kind code	A1
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

First claim

What is claimed is:

1 . A radio transceiver comprising:
a coarse tuning circuit operable to generate a coarse tune failure indicator; a frequency target lock detector circuit operable to generate a frequency target failure indicator; a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator; and a transceiver sequence manager communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the transceiver sequence manager operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

2 . The radio transceiver of claim 1 , wherein the cycle slip monitor circuit comprises an analog cycle slip event detector circuit and a digital cycle slip event detector circuit.

3 . The radio transceiver of claim 1 , wherein the cycle slip lock failure indicator comprises an indicator that a plurality of cycle slip events have occurred within a predetermined time frame.

4 . The radio transceiver of claim 2 , wherein the digital cycle slip lock detector circuit is operable to:
monitor cycle slips; generate a count of cycle slip events; if the count is below a threshold, mask cycle slip events for a predetermined masking time; if the count is above the threshold, set the cycle slip lock failure indicator; and generate a signal associated with disabling the analog cycle slip lock detector circuit when monitoring is paused.

5 . The radio transceiver of claim 1 , wherein the transceiver sequence manager is further operable to generate the radio operation abort indicator based at least on the coarse tune failure indicator prior to the radio transceiver entering a phase lock loop locking phase.

6 . The radio transceiver of claim 1 , wherein the transceiver sequence manager is further operable to generate the radio operation abort indicator based at least on the frequency target failure indicator prior to the radio transceiver entering an active radio operation.

7 . The radio transceiver of claim 1 , wherein the transceiver sequence manager further comprises:
a receive mode logic circuit operable to generate a first abort logic signal based at least on the radio operation abort indicator, a receive mode indicator, and a receive mode abort disable indicator; a transmit mode logic circuit operable to generate a second abort logic signal based at least on the radio operation abort indicator, a transmit mode indicator, and a transmit mode abort disable indicator; and a logic circuit [ 306 ] operable to generate an abort indicator based at least on the first and second abort logic signals.

8 . The radio transceiver of claim 1 , wherein the transceiver sequence manager is further operable to communicate to a processor that operation of the radio has been aborted.

9 . A phase lock loop monitor circuit comprising:
a coarse tuning circuit operable to generate a coarse tune failure indicator; a frequency target lock detector circuit operable to generate a frequency target failure indicator; a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator; and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

10 . The phase lock loop monitor circuit of claim 9 , wherein the cycle slip monitor circuit comprises an analog cycle slip event detector circuit and a digital cycle slip event detector circuit.

11 . The phase lock loop monitor circuit of claim 9 , wherein the cycle slip lock failure indicator comprises an indicator that a plurality of cycle slip events have occurred within a predetermined time frame.

12 . The phase lock loop monitor circuit of claim 10 , wherein the digital cycle slip lock detector circuit is operable to:
monitor cycle slips; generate a count of cycle slip events; if the count is below a threshold, mask cycle slip events for a predetermined masking time; if the count is above the threshold, set the cycle slip lock failure indicator; and generate a signal associated with disabling the analog cycle slip lock detector circuit when monitoring is paused.

13 . The phase lock loop monitor circuit of claim 9 , wherein the abort logic circuit is operable to communicate the radio operation abort indicator to a transceiver sequence manager, wherein the transceiver sequence manager is operable to generate an abort indicator based at least on the coarse tune failure indicator prior to the radio transceiver entering a phase lock loop locking phase.

14 . The phase lock loop monitor circuit of claim 9 , wherein the abort logic circuit is operable to communicate the radio operation abort indicator to a transceiver sequence manager, wherein the transceiver sequence manager is operable to generate an abort indicator based at least on the frequency target failure indicator prior to the radio transceiver entering an active radio operation.

15 . The phase lock loop monitor circuit of claim 13 , wherein the transceiver sequence manager further comprises:
a receive mode logic circuit operable to generate a first abort logic signal based at least on the radio operation abort indicator, a receive mode indicator, and a receive mode abort disable indicator; a transmit mode logic circuit operable to generate a second abort logic signal based at least on the radio operation abort indicator, a transmit mode indicator, and a transmit mode abort disable indicator; and a logic circuit operable to generate an abort indicator based at least on the first and second abort logic signals.

16 . The phase lock loop monitor circuit of claim 14 , wherein the transceiver sequence manager further comprises:
a receive mode logic circuit operable to generate a first abort logic signal based at least on the radio operation abort indicator, a receive mode indicator, and a receive mode abort disable indicator; a transmit mode logic circuit operable to generate a second abort logic signal based at least on the radio operation abort indicator, a transmit mode indicator, and a transmit mode abort disable indicator; and a logic circuit operable to generate an abort indicator based at least on the first and second abort logic signals.

17 . A method for monitoring cycle slips in a radio transceiver, the method comprising:
monitoring cycle slip events within a predetermined monitoring window; upon receiving a cycle slip event indication from an analog cycle slip event detector circuit, updating a count of cycle slip events; if the count is below a threshold, masking cycle slip events for a predetermined masking time; if the count is above the threshold, setting a cycle slip lock failure indicator; upon expiration of the predetermined monitored window, suspending monitoring; and upon expiration of a predetermined low power wait time, resuming monitoring.

18 . The method of claim 17 , further comprising generating a signal associated with a suspension of the analog cycle slip event detector circuit when suspending monitoring.

19 . The method of claim 17 , further comprising clearing the cycle slip lock failure indicator and subsequently resuming monitoring.

Assignees

• Freescale Semiconductor Inc

Inventors

• Stoll Chris N
• Behera Prachee S
• Brown David F
• Kythakyapuzha Shobak R
• Waheed Khurram

Classifications

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04B1/40

  Circuits · CPC title

• H04B3/46 Primary

  Monitoring; Testing · CPC title

• H04J3/1652

  Optical Transport Network [OTN] · CPC title