Method for separating regions of a semiconductor layer

Patent metadata

Field	Value
Publication number	US-9865776-B2
Application number	US-201715413281-A
Country	US
Kind code	B2
Filing date	Jan 23, 2017
Priority date	Sep 27, 2012
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

The invention relates to a method for separating regions of a semiconductor layer and for introducing an outcoupling structure into an upper side of the semiconductor layer, the outcoupling structure being provided to couple light out of the semiconductor layer. The upper side of the semiconductor layer is covered by a mask having first openings for introducing the outcoupling structure and at least a second opening, which is provided to introduce a separating trench into the semiconductor layer. With the aid of an etching method, the outcoupling structure is introduced into the upper side of the semiconductor layer in the region of the first openings and simultaneously a separating trench passing through the semiconductor layer is introduced into the semiconductor layer via the second opening, and a region of the semiconductor layer is separated.

First claim

The invention claimed is:

1. An optoelectronic semiconductor chip, comprising:
a semiconductor layer having an active zone for generating light;
a coupling-out structure for coupling out light;
a separating trench around a region of the semiconductor layer; and
a circumferential etched edge region,
wherein the separating trench is introduced over the entire thickness of the semiconductor layer.

2. The optoelectronic semiconductor chip according to claim 1 , wherein the coupling-out structure is roughened and in a central region, and
wherein the central region is surrounded by a non-roughened edge region.

3. The optoelectronic semiconductor chip according to claim 1 , wherein the top side of the semiconductor layer is provided with a coupling-out structure by means of an etched surface.

4. The optoelectronic semiconductor chip according to claim 1 , wherein the semiconductor layer comprises an epitaxially applied layer at least at the top side.

5. The optoelectronic semiconductor chip according to claim 1 , wherein the semiconductor layer comprises at least one active layer on the basis of InGaAlN.

6. The optoelectronic semiconductor chip according to claim 1 , wherein the semiconductor layer comprises at least one GaN layer.

7. The optoelectronic semiconductor chip according to claim 1 , wherein the coupling out structure comprises cutouts in the semiconductor layer.

8. The optoelectronic semiconductor chip according to claim 7 , wherein the cutouts have pyramidal depressions.

9. The optoelectronic semiconductor chip according to claim 8 , wherein the base of a pyramidal cutout has a hexagonal shape.

10. An optoelectronic semiconductor chip, comprising:
a semiconductor layer having an active zone for generating light;
a roughened coupling-out structure in a central region for coupling out light;
a separating trench around a region of the semiconductor layer; and
a circumferential etched edge region,
wherein the central region is surrounded by a non-roughened edge region.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Zini Lorenzo
• Boehm Bernd

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L33/24 Primary

  Electricity · mapped topic

• H01L25/167

  Electricity · mapped topic

• H01L33/0095

  Electricity · mapped topic

• H01L33/20

  Electricity · mapped topic