Method for separating regions of a semiconductor layer

Patent metadata

Field	Value
Publication number	US-9589943-B2
Application number	US-201314430872-A
Country	US
Kind code	B2
Filing date	Sep 26, 2013
Priority date	Sep 27, 2012
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

The invention relates to a method for separating regions of a semiconductor layer and for introducing an outcoupling structure into an upper side of the semiconductor layer, the outcoupling structure being provided to couple light out of the semiconductor layer. The upper side of the semiconductor layer is covered by a mask having first openings for introducing the outcoupling structure and at least a second opening, which is provided to introduce a separating trench into the semiconductor layer. With the aid of an etching method, the outcoupling structure is introduced into the upper side of the semiconductor layer in the region of the first openings and simultaneously a separating trench passing through the semiconductor layer is introduced into the semiconductor layer via the second opening, and a region of the semiconductor layer is separated.

First claim

The invention claimed is:

1. A method for separating regions of a semiconductor layer having an active zone for generating light and for introducing a coupling-out structure into a top side of the semiconductor layer,
wherein the coupling-out structure is provided in order to couple out light from the semiconductor layer,
wherein the top side of the semiconductor layer is covered with a mask,
wherein the mask has first openings for introducing the coupling-out structure,
wherein the mask has at least one second opening,
wherein the second opening is provided in order to introduce a separating trench around a region of the semiconductor layer,
wherein the coupling-out structure is simultaneously introduced into the top side of the semiconductor layer via the first openings with the aid of an etching method, and
wherein the second opening is chosen with a size such that the separating trench is simultaneously introduced in the region of the second opening over the entire thickness of the semiconductor layer and a region of the semiconductor layer is thus separated.

2. The method according to claim 1 , wherein the separated region of the semiconductor layer has a roughened central region surrounded by a smooth, non-roughened edge.

3. The method according to claim 1 , wherein a mask having a substantially identical thickness in the region of the first and the second openings is used.

4. The method according to claim 1 , wherein a gaseous or liquid etching medium is used as etchant.

5. The method according to claim 1 , wherein the semiconductor layer comprises an epitaxially applied layer at least at the top side.

6. The method according to claim 1 , wherein the semiconductor layer comprises at least one GaN layer.

7. The method according to claim 1 , wherein the mask is removed and, in a further etching step, the previously covered regions of the top side of the semiconductor layer are also provided with a coupling-out structure by means of an etching method.

8. The method according to claim 1 , wherein the separated region of the semiconductor layer constitutes a semiconductor chip, in particular an LED semiconductor chip.

9. An optoelectronic semiconductor chip having a semiconductor layer having an active zone for generating light, having a coupling-out structure for coupling out light having a circumferential etched edge region, wherein the coupling-out structure and the circumferential edge region were produced according to a method according to claim 1 .

10. The semiconductor chip according to claim 9 , wherein a central region has the roughened coupling-out structure, wherein the central region is surrounded by a non-roughened edge region.

11. The method according to claim 1 , wherein a hard mask is used as the mask.

12. The method according to claim 11 , wherein the hard mask is a resist mask.

13. The method according to claim 1 , wherein the etching method is a dry etching method.

14. The method according to claim 13 , wherein a plasma is used in the dry etching method.

15. A method for separating regions of a semiconductor layer having an active zone for generating light and for introducing a coupling-out structure into a top side of the semiconductor layer,
wherein the coupling-out structure is provided in order to couple out light from the semiconductor layer,
wherein the top side of the semiconductor layer is covered with a mask,
wherein the mask has first openings for introducing the coupling-out structure,
wherein the mask has a plurality of second openings,
wherein the second openings are provided in order to introduce a separating trench around a region of the semiconductor layer,
wherein the coupling-out structure is simultaneously introduced into the top side of the semiconductor layer via the first openings with the aid of an etching method,
wherein the second openings are chosen with a size such that the separating trench is simultaneously introduced in the region of the second openings over the entire thickness of the semiconductor layer and a region of the semiconductor layer is thus separated,
wherein the mask has first mask elements and second mask elements,
wherein the first openings are in each case provided between a first mask element and a further first mask element or between a first mask element and a second mask element,
wherein a width of the second mask elements is greater than a width of the first mask elements, and
wherein the second openings are provided between two second mask elements.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Zini Lorenzo
• Boehm Bernd

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L25/167 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L33/20

  Electricity · mapped topic