Horizontal gate all around and FinFET device isolation

Patent metadata

Field	Value
Publication number	US-9865735-B2
Application number	US-201615152273-A
Country	US
Kind code	B2
Filing date	May 11, 2016
Priority date	May 11, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

First claim

What is claimed is:

1. A device structure, comprising:
a substrate;
a channel structure formed on the substrate, the channel structure having one or more silicon material layers, one or more silicon germanium material layers comprising between about 20% and about 40% germanium, and a buried oxide layer, wherein the silicon material layers, the silicon germanium material layers, and the buried oxide layer are disposed in a stacked arrangement.

2. The device structure of claim 1 , wherein the buried oxide layer is disposed between the silicon germanium material layers in the stacked arrangement.

3. The device structure of claim 2 , further comprising:
a liner formed on sidewalls of the channel structure, wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

4. A device structure, comprising:
a channel structure having one or more silicon material layers, one or more silicon germanium material layers comprising between about 20% and about 40% germanium, and a buried oxide layer, wherein the silicon material layers, the silicon germanium material layers, and the buried oxide layer are disposed in a stacked arrangement.

5. The device structure of claim 4 , wherein the buried oxide layer is disposed between the silicon germanium material layers in the stacked arrangement.

6. The device structure of claim 5 , further comprising:
a liner formed on sidewalls of the channel structure, wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

7. The device structure of claim 4 , further comprising:
a liner formed on sidewalls of the channel structure.

8. The device structure of claim 7 , wherein the liner is an oxynitride material, a silicon nitride materials, or combinations thereof.

9. A device structure, comprising:
a substrate;
a channel structure formed on the substrate, the channel structure having one or more silicon material layers, one or more silicon germanium material layers comprising between about 20% and about 40% germanium, and a buried oxide layer, wherein the silicon material layers, the silicon germanium material layers, and the buried oxide layer are disposed in a stacked arrangement;
source/drain regions formed on the substrate; and
a metal gate structure formed over the channel structure.

10. The device structure of claim 9 , wherein the buried oxide layer is disposed between the silicon germanium material layers in the stacked arrangement.

11. The device structure of claim 9 , further comprising:
a liner formed on sidewalls of the channel structure, wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

12. A device structure, comprising:
a substrate;
a channel structure having a buried oxide layer disposed on and in contact with the substrate and a silicon layer or silicon germanium layer comprising between about 20% and about 40% germanium disposed on the buried oxide layer;
source/drain regions formed on the substrate; and
a metal gate structure formed over the silicon layer or silicon germanium layer.

13. The device structure of claim 12 , wherein the source/drain regions are formed from a material selected from the group consisting of silicon, phosphorous doped silicon, silicon germanium, germanium, and combinations thereof.

14. The device structure of claim 12 , wherein the metal gate structure is formed from a materials selected from the group consisting of hafnium dioxide, zirconium dioxide, titanium dioxide, titanium nitride, titanium aluminide, nitride materials, and combinations thereof.

Assignees

• Applied Materials Inc

Inventors

• Sun Shiyu
• Yoshida Naomi
• Guarini Theresa Kramer
• Jun Sung Won
• PENA Vanessa
• Sanchez Errol Antonio C
• Colombeau Benjamin
• Chudzik Michael
• Wood Bingxi
• Kim Nam Sung

Classifications

• H01L29/1054

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic