Extremely large spin hall angle in topological insulator pn junction

Patent metadata

Field	Value
Publication number	US-9865713-B2
Application number	US-201514871923-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	May 31, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

The interplay between chiral tunneling and spin-momentum locking of helical surface states leads to spin amplification and filtering in a 3D Topological Insulator (TI). Chiral tunneling across a TI pn junction allows normally incident electrons to transmit, while the rest are reflected with their spins flipped due to spin-momentum locking. The net result is that the spin current is enhanced while the dissipative charge current is simultaneously suppressed, leading to an extremely large, tunable longitudinal spin Hall angle (˜20) at the reflected end. At the transmitted end, the angle stays close to one and the electrons are completely spin polarized.

First claim

What is claimed is:

1. An electronic device comprising a topological insulator pn junction,
the topological insulator pn junction including:
a source;
a drain; and
a plurality of gates,

wherein a chiral tunneling directs a movement of a plurality of electrons in the topological insulator pn junction.

2. The electronic device according to claim 1 , wherein
the plurality of gates are spatially separated.

3. The electronic device according to claim 1 , wherein
the topological insulator has helical states, wherein in the helical states, spin and momentum of the plurality of electrons are locked.

4. The electronic device according to claim 1 , wherein
the topological insulator is a class of materials including Bi 2 Se 3 and Bi 2 Te 3 .

5. The electronic device according to claim 1 , wherein
the topological insulator has a bulk bandgap.

6. The electronic device according to claim 1 , wherein
the chiral tunneling across the topological insulator pn junction allows a part of the plurality of electrons to transmit through the drain and rest of the plurality of electrons to reflect back to the source.

7. The electronic device according to claim 6 , wherein
spins of the reflected electrons are flipped due to spin-momentum locking.

8. The electronic device according to claim 6 , wherein
the transmitted electrons have very small incident angle.

9. The electronic device according to claim 6 , wherein
a charge current going through the topological insulator pn junction is suppressed and a spin current at the source is amplified.

10. The electronic device according to claim 9 , wherein
a suppression of the charge current and an amplification of the spin current are done simultaneously.

11. The electronic device according to claim 6 , wherein
the chiral tunneling in the topological insulator pn junction results in a gate tunable, a large spin-charge current gain at a reflected end of the topological insulator pn junction.

12. The electronic device according to claim 11 , wherein
the gain at the reflected end is approximately 20.

13. The electronic device according to claim 11 , wherein
the gain at the reflected end, β, for small grain bias is defined as:

β
≈

1
+

R
av

1
-

R
av

≈

π
⁢

q
⁢

⁢

V
o

⁢
d

ℏ
⁢

⁢

v
F

,

wherein R av is a reflection probability averaged over all modes, V o is a built in potential of the topological insulator pn junction, and d is a split between the plurality of gates.

14. The electronic device according to claim 11 , wherein
the gain at the reflected end, β, for large bias is approximated as:

β
≈

2
⁢

q
⁢

⁢

V
o

⁢
d

ℏ
⁢

⁢

v
F

,

wherein V o is a built in potential of the topological insulator pn junction, and d is a split between the plurality of gates.

15. The electronic device according to claim 6 , wherein
a gain at a transmitted end of the topological insulator pn junction is close to one.

16. The electronic device according to claim 6 , wherein
the transmitted electrons are completely spin polarized at a transmitted end.

17. The electronic device according to claim 1 , wherein
flows of spin and charge are parallel.

18. A topological insulator pn junction comprising:
a source;
a drain; and
a plurality of gates,

wherein a chiral tunneling directs a movement of a plurality of electrons in the topological insulator pn junction.

Assignees

• Univ Virginia Patent Foundation

Inventors

• Habib K M Masum
• Sajjad Redwan Noor
• Ghosh Avik

Classifications

• H01L27/098

  Electricity · mapped topic

• H01L29/66984 Primary

  Electricity · mapped topic

• H01L29/0843

  Electricity · mapped topic

• H01L29/42312

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic