High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process

Patent metadata

Field	Value
Publication number	US-9865703-B2
Application number	US-201514985733-A
Country	US
Kind code	B2
Filing date	Dec 31, 2015
Priority date	Dec 31, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate having an outer surface;
a plurality of metal gate stacks located outward of said outer surface of said semi conductor substrate;
a plurality of oxide regions, located outward of said outer surface of said semiconductor substrate, and interspersed between said plurality of metal gate stacks;
a liner interspersed between said plurality of oxide regions and said semiconductor substrate and between said plurality of oxide regions and said plurality of metal gate stacks; and
a plurality of high-K layers separating said plurality of metal gate stacks from said semiconductor substrate and disposed between said plurality of metal gate stacks and said plurality of oxide regions;
wherein:
said plurality of oxide regions and said plurality of metal gate stacks extend outwardly to a first height from said semiconductor substrate; and
said plurality of high-K layers extend outwardly to a second height from said semiconductor substrate, said second height being less than said first height;
further comprising a plurality of FINS protruding from said substrate between said plurality of oxide regions and intermediate said plurality of high-K layers and said substrate, wherein said second height is such that said plurality of high-K layers extend outwardly beyond said plurality of FINS.

2. The structure of claim 1 , wherein said substrate comprises a silicon-on-insulator substrate.

3. The structure of claim 1 , wherein said substrate comprises a bulk substrate.

4. The structure of claim 1 , wherein said oxide regions comprise silicon dioxide.

5. The structure of claim 1 , wherein said oxide regions comprise flowable oxide.

6. The structure of claim 1 , wherein said liner comprises silicon nitride.

7. The structure of claim 1 , wherein said high-K layers comprise a metal oxide with a dielectric constant greater than that of silicon dioxide.

Assignees

• IBM

Inventors

• Ando Takashi
• Basker Veeraraghavan S
• Faltermeier Johnathan E
• Jagannathan Hemanth
• Yamashita Tenko

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6925

  the material comprising hydrogen silsesquioxane, e.g. HSQ · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title