Poly sandwich for deep trench fill

Patent metadata

Field	Value
Publication number	US-9865691-B2
Application number	US-201715403748-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Nov 26, 2014
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising the steps:
providing a substrate comprising a semiconductor material;
forming a trench at least 10 microns deep in the substrate;
forming a dielectric liner on sidewalls of the trench;
forming a first layer of polysilicon on the dielectric liner so that the first layer of polysilicon extends into the trench, the first layer of polysilicon being formed as an undoped layer;
implanting dopants into the first layer of polysilicon;
forming a second layer of polysilicon on the first layer of polysilicon so that the second layer of polysilicon extends into the trench, the second layer of polysilicon being formed as an undoped layer; and
annealing the substrate so as to activate and diffuse the implanted dopants, so that an average doping density in the first layer of polysilicon and the second layer of polysilicon is at least 1×10 18 cm −3 .

2. The method of claim 1 , wherein the dopants are implanted at a dose of 2×10 15 cm −2 to 1×10 16 cm −2 .

3. The method of claim 1 , wherein the dopants are implanted in 4 sub-doses at tilt angles of 1 degree to 2 degrees and twist angles of about zero degrees.

4. The method of claim 1 , wherein the first layer of polysilicon has a thickness of 150 nanometers to 200 nanometers.

5. The method of claim 1 , wherein the step of annealing the substrate includes a furnace anneal at 1000° C. to 1100° C. for 100 minutes to 150 minutes in a nitrogen ambient.

6. The method of claim 1 , comprising forming a buried layer in the substrate prior to forming the trench, so that the trench extends below a bottom surface of the buried layer.

7. The method of claim 1 , wherein forming the dielectric liner includes forming a layer of thermal oxide on the sidewalls and forming a layer of deposited silicon dioxide on the layer of thermal oxide.

8. The method of claim 1 , comprising removing the dielectric liner at a bottom of the trench prior to forming the first layer of polysilicon, and forming the first layer of polysilicon to extend to a bottom of the trench so that the first layer of polysilicon makes an electrical contact to the substrate at the bottom of the trench.

9. The method of claim 8 , comprising implanting dopants into the semiconductor material of the substrate at the bottom of the trench, after removing the dielectric liner at a bottom of the trench and prior to forming the first layer of polysilicon.

10. The method of claim 1 , wherein the first layer of polysilicon is formed extending to a bottom of the trench so that the dielectric liner isolates the first layer of polysilicon from the substrate.

11. A method of forming a semiconductor device, comprising the steps:
providing a substrate comprising a semiconductor material;
forming a trench at least 10 microns deep in the substrate;
forming a dielectric liner on sidewalls of the trench;
removing the dielectric liner at a bottom of the trench;
implanting dopants into the semiconductor material of the substrate at the bottom of the trench;
forming a first layer of polysilicon on the dielectric liner, extending to a bottom of the trench so that the first layer of polysilicon makes an electrical contact to the substrate at the bottom of the trench, the first layer of polysilicon being formed as an undoped layer;
implanting dopants into the first layer of polysilicon;
forming a second layer of polysilicon on the first layer of polysilicon so that the second layer of polysilicon extends into the trench, the second layer of polysilicon being formed as an undoped layer; and
annealing the substrate so as to activate and diffuse the implanted dopants, so that an average doping density in the first layer of polysilicon and the second layer of polysilicon is at least 1×10 18 cm −3 .

12. The method of claim 11 , wherein forming the dielectric liner includes forming a layer of thermal oxide on the sidewalls and forming a layer of deposited silicon dioxide on the layer of thermal oxide.

13. The method of claim 11 , comprising forming a buried layer in the substrate prior to forming the trench, so that the trench extends below a bottom surface of the buried layer.

Assignees

• Texas Instruments Inc

Inventors

• Hu Binghua
• Pendharkar Sameer P
• Jacobs Jarvis Benjamin

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title