Three-dimensional semiconductor memory devices including a vertical channel

Patent metadata

Field	Value
Publication number	US-9865685-B2
Application number	US-201715403440-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Apr 21, 2014
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of gate electrodes stacked on a substrate;
an active pillar extending through the plurality of gate electrodes; and
a gate insulating layer disposed between the active pillar and the plurality of gate electrodes,
wherein the active pillar includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a sidewall of the gate insulating layer,
wherein the first semiconductor layer comprises a single crystalline material or silicon-germanium (SiGe), and
wherein a germanium content of the first semiconductor layer is higher than a silicon content of the first semiconductor layer.

2. The semiconductor memory device of claim 1 , wherein the second semiconductor layer includes silicon, and
wherein the silicon content of the first semiconductor layer is lower than a silicon content of the second semiconductor layer.

3. The semiconductor memory device of claim 1 , wherein the second semiconductor layer includes silicon-germanium (SiGe), and
wherein the germanium content of the first semiconductor layer is higher than a germanium content of the second semiconductor layer.

4. The semiconductor memory device of claim i, wherein the second semiconductor layer has an amorphous structure, a single crystalline structure, or a poly-crystalline structure.

5. The semiconductor memory device of claim 1 , wherein the second semiconductor layer is a silicon layer, a silicon-germanium layer, or a silicon-carbide layer.

6. The semiconductor memory device of claim 1 , wherein the gate insulating layer is closer to, the first semiconductor layer than the second semiconductor layer.

7. The semiconductor memory device of claim 1 , wherein the first semiconductor layer is in contact with the substrate, and
wherein the second semiconductor layer is spaced apart from the substrate.

8. The semiconductor memory device of claim 1 , wherein the active pillar further comprises a third semiconductor layer on a sidewall of the second semiconductor layer,
wherein the second semiconductor layer includes silicon-germanium (SiGe), and
wherein the third semiconductor layer is a silicon layer.

9. The semiconductor memory device of claim 1 , wherein the first semiconductor layer has ‘L’ shape.

10. The semiconductor memory device of claim 1 , wherein the gate insulating layer comprises:
a blocking insulating layer between the first semiconductor layer and the plurality of gate electrodes;
a tunnel insulating layer between the first semiconductor layer and the blocking insulating layer; and
a charge storage layer between the blocking insulating layer and the tunnel insulating layer.

11. A semiconductor memory device comprising:
a plurality of gate electrodes stacked on a substrate;
an active pillar extending through the plurality of gate electrodes; and
a gate insulating layer disposed between the active pillar and the plurality of gate electrodes,
wherein the active pillar includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a sidewall of the gate insulating layer,
wherein the first semiconductor layer comprises a single crystalline material ,or silicon-germanium (SiGe),
wherein the active pillar further comprises a third semiconductor layer on a sidewall of the second semiconductor layer,
wherein the second semiconductor layer includes silicon-germanium (SiGe), and
wherein the third semiconductor layer is a silicon layer.

12. The semiconductor memory device of claim 11 , wherein a germanium content of the first semiconductor layer is higher than a germanium content of the second semiconductor layer.

13. The semiconductor memory device of claim 11 , wherein the first semiconductor layer includes silicon, and
wherein a silicon content of the first semiconductor layer is lower than a silicon content of the second semiconductor layer.

14. The semiconductor memory device of claim 11 , wherein the first semiconductor layer comprises silicon-germanium, and a germanium content of the first semiconductor layer is equal to or greater than 50%, and
wherein a germanium content of the second semiconductor layer is less than 50%.

15. A semiconductor memory device comprising:
a plurality of gate electrodes stacked on a substrate;
an active pillar extending through the plurality of gate electrodes; and
a gate insulating layer extending between the active pillar and the plurality of gate electrodes,
wherein the active pillar includes a first semiconductor layer and a second semiconductor layer sequentially stacked on the gate insulating layer,
wherein the second semiconductor layer comprises a material different from the, first semiconductor layer,
wherein the first semiconductor layer comprises a single crystalline material or silicon-germanium (SiGe), and
wherein a germanium content of the first semiconductor layer is higher than a germanium content of the second semiconductor layer.

16. The semiconductor memory device of claim 15 , wherein the first semiconductor layer comprises silicon-germanium, and the germanium content of the first semiconductor layer is equal to or greater than 50%, and
wherein the second semiconductor layer comprises silicongermanium, and the germanium content of the second semiconductor layer is less than 50%.

17. The semiconductor memory device of claim 15 , wherein the active pillar further comprises a third semiconductor layer on the second semiconductor layer,
wherein the second semiconductor layer extends between the first semiconductor layer and the third semiconductor layer, and
wherein the third semiconductor layer comprises a silicon layer.

18. The semiconductor memory device of claim 15 , wherein the second semiconductor layer comprises a silicon layer, a silicon-germanium layer, or a silicon-carbide layer.

19. The semiconductor memory device of claim 15 , wherein the first semiconductor layer comprises germanium (Ge), gallium-arsenic (GaAs), indium-gallium-arsenic (InGaAs), and/or aluminum-gallium-arsenic (AlGaAs).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sim Jaesung
• Park Youngwoo

Classifications

• H01L29/165

  Electricity · mapped topic

• H01L29/04

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic

• H01L29/1037 Primary

  Electricity · mapped topic