High voltage field balance metal oxide field effect transistor (FBM)

Patent metadata

Field	Value
Publication number	US-9865678-B2
Application number	US-201615236263-A
Country	US
Kind code	B2
Filing date	Aug 12, 2016
Priority date	Aug 25, 2011
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device includes a semiconductor substrate and epitaxial layer of a first conductivity type with the epitaxial layer on a top surface of the substrate. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the epitaxial layer. A first conductivity type source region is inside the body region and a drain is at a bottom surface of the substrate. An inslated gate overlaps the source and body regions. First and second trenches in the epitaxial layer are lined with insulation material and filled with electrically conductive material. Second conductivity type buried regions are positioned below the trenches. Second conductivity type charge linking paths along one or more walls of the first trench electrically connect a first buried region to the body region. A second buried region is separated from the body region by portions of the expitaxial layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type;
an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate;
a body region of a second conductivity type that is opposite of the first conductivity type disposed near a top surface of the epitaxial layer;
a source region of the first conductivity type disposed near the top surface of the epitaxial layer inside the body region;
a drain disposed at a bottom surface of the semiconductor substrate:
a gate overlapping a portion of the source region and a portion of the body region having a gate insulation layer separating the gate from the source region and the body region;
first and second trenches formed in the epitaxial layer on opposite sides of the gate, wherein the first and second trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material;
a first buried doped region of the second conductivity type positioned below the first trench;
one or more charge linking paths of the second conductivity type positioned along one or more trench walls of the first trench and configured to electrically connect the first buried doped region to the body region; and
a second buried doped region of the second conductivity type positioned below the second trench, wherein portions of the expitaxial layer separate the second buried doped region from the body region.

2. The device of claim 1 , wherein the electrically conductive trench filling material in the first trench is configured to be in electrical contact with a source electrode on top of the epitaxial layer and in electrical contact with the source region.

3. The device of claim 1 , wherein the electrically conductive trench filling material in the second trench is configured to be in electrical contact with the gate.

4. The device of claim 1 , wherein the one or more charge linking paths are formed by diffusion.

5. The device of claim 1 , wherein the gate is formed on the top surface of the epitaxial layer.

6. The device of claim 1 , wherein the second buried doped region is electrically connected to the body region.

7. The device of claim 1 , wherein the first and second buried doped regions are lighter doped than the body region.

8. The device of claim 1 , wherein the epitaxial layer includes a surface shielded region positioned above a voltage blocking region, wherein the surface shielded region is more heavily doped than the voltage blocking region.

9. The device of claim 1 , wherein the first and second buried doped regions extend to a depth substantially the same as a bottom surface of the surface shielded region.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bhalla Anup
• Yilmaz Hamza
• Bobde Madhur
• Guan Lingpeng
• Hu Jun
• Kim Jongoh
• Ding Yongping

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H01L29/0615

  Electricity · mapped topic