Array substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9865619-B2
Application number	US-201514779545-A
Country	US
Kind code	B2
Filing date	Aug 13, 2015
Priority date	Aug 10, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer.

First claim

The invention claimed is:

1. A manufacturing method of an array substrate, comprising steps of:
forming a buffer layer on a substrate;
forming a whole light-shading layer on the buffer layer, wherein the material of the light-shading layer is an amorphous silicon;
oxidizing the light-shading layer, so as to form an insulation film on the light-shading layer;
forming a whole semiconductor layer on the insulation film, and simultaneously patterning the semiconductor layer and the light-shading layer, wherein portions of the light-shading layer and portions of the semiconductor layer are covered on the buffer layer in order;
and the semiconductor layer is configured to form a channel;
forming a first insulation layer on the patterned semiconductor layer;
forming a first metal layer on the first insulation layer, wherein the first metal layer is patterned to form gate electrodes and common electrodes;
forming a second insulation layer on the first metal layer;
disposing a third via on the second insulation layer which corresponds to the common electrodes, wherein the second metal layer is contacted with the common electrodes;
forming a second metal layer on the second insulation layer, wherein the second metal layer is patterned to form drain electrodes and source electrodes;
forming a flat layer on the second metal layer and the second insulation layer uncovered by the second metal layer, wherein a first via is formed on the flat layer; and
forming a first transparent conductive layer on the flat layer, wherein the first transparent conductive layer is connected with the second metal layer through the first via.

2. The manufacturing method of the array substrate according to claim 1 , wherein after the step of forming the first metal layer on the first insulation layer, the method further comprises:
doping a first trigger-conductivity material into a first portion of the patterned semiconductor layer by means of diffusion or ion implantation; wherein the first trigger-conductivity material is configured to increase the conductivity of the semiconductor layer; the density of the first trigger-conductivity material in the patterned semiconductor layer is greater than a first default density; and the first portion is a portion of the patterned semiconductor layer which is uncovered by the gate electrodes.

3. The manufacturing method of the array substrate according to claim 2 , wherein the method further comprises:
etching the gate electrodes further, so as to decrease the area of the gate electrodes covering the semiconductor layer; and
doping a second trigger-conductivity material into a second portion of the patterned semiconductor layer by means of diffusion or ion implantation; wherein the second trigger-conductivity material is configured to increase the conductivity of the semiconductor layer; the density of the second trigger-conductivity material in the patterned semiconductor layer is less than a second default density; and the second portion is a portion of the patterned semiconductor layer which is uncovered by the etched gate electrodes and no overlap with the first portion.

4. The manufacturing method of the array substrate according to claim 1 , wherein after the step of forming the second metal layer on the second insulation layer, the method further comprises:
disposing a second via on the second insulation layer and the first insulation layer; wherein the source electrodes and the drain electrodes are connected with the semiconductor layer through the second via.

5. The manufacturing method of the array substrate according to claim 1 , wherein the material of the insulation film is silica (SiO 2 ).

6. The manufacturing method of the array substrate according to claim 1 , wherein before the step of forming the flat layer on the second metal layer and the second insulation layer uncovered by the second metal layer, the method further comprises:
forming a second transparent conductive layer on the second metal layer which corresponds to the common electrodes.

7. The manufacturing method of the array substrate according to claim 1 , wherein the first transparent conductive layer includes pixel electrodes.

8. The manufacturing method of the array substrate according to claim 1 , wherein the material of the semiconductor layer is a low temperature poly-silicon (LTPS).

9. A manufacturing method of an array substrate, comprising steps of:
forming a buffer layer on a substrate;
forming a whole light-shading layer on the buffer layer;
forming a whole semiconductor layer on the light-shading layer, and simultaneously patterning the semiconductor layer and the light-shading layer, wherein portions of the light-shading layer and portions of the semiconductor layer are covered on the buffer layer in order; and the semiconductor layer is configured to form a channel;
forming a first insulation layer on the patterned semiconductor layer;
forming a first metal layer on the first insulation layer, wherein the first metal layer is patterned to form gate electrodes and common electrodes;
forming a second insulation layer on the first metal layer;
forming a second metal layer on the second insulation layer, wherein the second metal layer is patterned to form drain electrodes and source electrodes;
forming a flat layer on the second metal layer and the second insulation layer uncovered by the second metal layer, wherein a first via is formed on the flat layer; and
forming a first transparent conductive layer on the flat layer, wherein the first transparent conductive layer is connected with the second metal layer through the first via.

10. The manufacturing method of the array substrate according to claim 9 , wherein after the step of forming the first metal layer on the first insulation layer, the method further comprises:
doping a first trigger-conductivity material into a first portion of the patterned semiconductor layer by means of diffusion or ion implantation; wherein the first trigger-conductivity material is configured to increase the conductivity of the semiconductor layer; the density of the first trigger-conductivity material in the patterned semiconductor layer is greater than a first default density; and the first portion is a portion of the patterned semiconductor layer which is uncovered by the gate electrodes.

11. The manufacturing method of the array substrate according to claim 10 , wherein the method further comprises:
etching the gate electrodes further, so as to decrease the area of the gate electrodes covering the semiconductor layer; and
doping a second trigger-conductivity material into a second portion of the patterned semiconductor layer by means of diffusion or ion implantation; wherein the second trigger-conductivity material is configured to increase the conductivity of the semiconductor layer; the density of the second trigger-conductivity material in the patterned semiconductor layer is less than a second default density; and the second portion is a portion of the patterned semiconductor layer which is uncovered by the etched gate electrodes and no overlap with the first portion.

12. The manufacturing method of the array substrate according to claim 9 , wherein after the step of forming the second metal layer on the second insulation layer, the method further comprises:
disposing a second via on the second insulation layer and the first insulation layer; wherein the source electrodes and the drain electrodes are connected with the semiconductor layer through the second via.

13. The manufacturing method of the array substrate according to claim 9 , wherein the material of the light-shading layer is a

Assignees

• Shenzhen China Star Optoelect

Inventors

• Wang Xiaoxiao
• Du Peng
• Wang Cong

Classifications

• H10P32/00

  Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title