Array substrate, method for manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-2016013210-A1
Application number	US-201414422334-A
Country	US
Kind code	A1
Filing date	Jul 9, 2014
Priority date	Sep 30, 2013
Publication date	Jan 14, 2016
Grant date	—

Abstract

A method for manufacturing an array substrate which includes: depositing a gate metal film on a base substrate, and forming a first pattern including the gate electrode by a first patterning process; depositing a gate insulating film, a first transparent conductive film, a source/drain metal film and a doped a-Si film sequentially, and forming a second pattern including the pixel electrode, the source electrode, the drain electrode and a doped semiconductor layer by a second patterning process; depositing an a-Si film, and forming a third pattern including a TFT channel, the semiconductor layer and a gate insulating layer via-hole by a third patterning process; depositing a passivation layer film, and forming a fourth pattern including a passivation layer via-hole by a fourth patterning process, the passivation layer via-hole being arranged at a position corresponding to the gate insulating layer via-hole; and depositing a second transparent conductive film on the base substrate with the fourth pattern, and forming a fifth pattern including an electrical connector by a fifth patterning process.

First claim

1 . A method for manufacturing an array substrate, the array substrate comprising a gate electrode, an active layer, a source electrode, a drain electrode and a pixel electrode, the method comprising:
Step 1: depositing a gate metal film on a base substrate, and forming a first pattern including the gate electrode by a first patterning process; Step 2: depositing a gate insulating film, a first transparent conductive film, a source/drain metal film and a doped a-Si film sequentially on the base substrate with the first pattern, and forming a second pattern including the pixel electrode, the source electrode, the drain electrode and a doped semiconductor layer by a second patterning process; Step 3: depositing an a-Si film on the base substrate with the second pattern, and forming a third pattern including a TFT channel, the semiconductor layer and a gate insulating layer via-hole by a third patterning process, the gate insulating layer via-hole being arranged at a position corresponding to the gate electrode; Step 4: depositing a passivation layer film on the base substrate with the third pattern, and forming a fourth pattern including a passivation layer via-hole by a fourth patterning process, the passivation layer via-hole being arranged at a position corresponding to the gate insulating layer via-hole; and Step 5: depositing a second transparent conductive film on the base substrate with the fourth pattern, and forming a fifth pattern including an electrical connector by a fifth patterning process, at least a portion of the electrical connector being located within the passivation layer via-hole and the gate insulating layer via-hole and configured to electrically connect the gate electrode and at least one of the source electrode and the drain electrode.

2 . The method according to claim 1 , wherein Step 1 comprises:
providing the base substrate; depositing the gate metal film on the base substrate; coating a photoresist onto the gate metal film; exposing and developing the photoresist with a mask, so as to at least reserve the photoresist at a position corresponding to the gate electrode; etching off, by a first etching process, the gate metal film which is not covered by the photoresist; and peeling off the remaining photoresist.

3 . The method according to claim 1 , wherein Step 2 comprises:
depositing the gate insulating film, the first transparent conductive film, the source/drain metal film and the doped a-Si film sequentially on the base substrate with the first pattern; coating a photoresist onto the doped a-Si film; exposing and developing the photoresist with a dual-tone mask so as to form a photoresist totally-remained region corresponding to the source electrode and the drain electrode, a photoresist half-remained region corresponding to the pixel electrode, and a photoresist totally-removed region corresponding to the regions other than the photoresist totally-remained region and the photoresist half-remained region, the photoresist totally-removed region including regions corresponding to the TFT channel and the gate insulating layer via-hole; etching off fully the first transparent conductive film, the source/drain metal film and the doped a-Si film at the photoresist totally-removed region by a second etching process; removing the photoresist at the photoresist half-remained region by an ashing process, so as to uncover the doped a-Si film at the photoresist half-remained region; etching off fully the doped a-Si film and the source/drain metal film at the photoresist half-remained region by a third etching process; and peeling off the remaining photoresist.

4 . The method according to claim 1 , wherein Step 3 comprises:
depositing the a-Si film on the base substrate with the second pattern; coating a photoresist onto the a-Si film; exposing and developing the photoresist with a mask so as to reserve the photoresist at a position corresponding to the active layer and remove the photoresist at a position corresponding to the gate insulating layer via-hole; etching off, by a fourth etching process, the a-Si film which is not covered by the photoresist, and etching the gate insulating layer at a position corresponding to the gate insulating layer via-hole by the fourth etching process; and peeling off the remaining photoresist.

5 . The method according to claim 1 , wherein Step 4 comprises:
depositing the passivation layer film on the base substrate with the third pattern; coating a photoresist onto the passivation layer film; exposing and developing the photoresist with a mask, and removing the photoresist at least at a position corresponding to the passivation layer via-hole, the passivation layer via-hole being arranged at a position corresponding to the gate insulating layer via-hole; etching off, by a fifth etching process, the passivation layer film which is not covered by the photoresist; and peeling off the remaining photoresist.

6 . The method according to claim 1 , wherein Step 5 comprises:
depositing the second transparent conductive film on the base substrate with the fourth pattern; coating a photoresist layer onto the second transparent conductive film; exposing and developing the photoresist with a mask so as to reserve the photoresist at least at a position corresponding to the passivation layer via-hole; etching off, by a sixth etching process, the second transparent conductive film which is not covered by the photoresist; and peeling off the remaining photoresist.

7 . The method according to claim 1 , wherein
in Step 5, a common electrode is also formed by the fifth patterning process while depositing the second transparent conductive film on the base substrate with the fourth pattern and forming the pattern including the electrical connector by the fifth patterning process.

8 . The method according to claim 7 , wherein Step 5 further comprises:
depositing the second transparent conductive film on the base substrate with the fourth pattern; coating a photoresist onto the second transparent conductive film; exposing and developing the photoresist with a mask so as to reserve the photoresist at least at positions corresponding to the common electrode and the passivation layer via-hole; etching off the second transparent conductive film by the sixth etching process; and peeling off the remaining photoresist.

9 . An array substrate, comprising:
a base substrate; a gate electrode formed on the base substrate; a gate insulating layer formed on the gate electrode and covering the entire base substrate, a gate insulating layer via-hole being provided in the gate insulating layer and located above at least a portion of the gate electrode; a pixel electrode formed on the gate insulating layer; a first transparent conductive portion arranged at a layer where the pixel electrode is located; a second transparent conductive portion arranged at a layer where the pixel electrode is located, the second transparent conductive portion and the first transparent conductive portion being located at both sides of the gate electrode, respectively; a source electrode arranged on the first transparent conductive portion; a drain electrode arranged on the second transparent conductive portion and at a layer where the source electrode is located, the source electrode and the drain electrode being arranged at both sides of the gate electrode, respectively, a TFT channel region being formed between a part of the source electrodes and the drain electrodes, and the gate insulating layer via-hole being arranged between the other part of the source electrodes and the drain electrodes; a doped semiconductor layer formed on the source electrode and the drain electrode,

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Opoelectronics Technology Co Ltd

Inventors

• Li Tiansheng
• Xie Zhenyu

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title