One-time-programming (OTP) memory cell with floating gate shielding

Patent metadata

Field	Value
Publication number	US-9865609-B2
Application number	US-201615008748-A
Country	US
Kind code	B2
Filing date	Jan 28, 2016
Priority date	Jan 28, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.

First claim

What is claimed is:

1. A memory cell with floating gate shielding, comprising:
a pair of transistors arranged on a semiconductor substrate and electrically coupled in series, wherein the transistors comprise a floating gate and a source/drain region bordering the floating gate;
an interconnect structure overlying the pair of transistors, wherein the interconnect structure comprises a conductive line and a conductive via, wherein the conductive via is under the conductive line, and wherein the conductive via extends continuously from contact with the source/drain region to contact with the conductive line; and
a shield arranged directly over the floating gate, in the interconnect structure, wherein the shield is configured to block ions in the interconnect structure from moving to the floating gate, wherein the shield is over an interface at which the conductive via contacts the conductive line, and wherein the shield is spaced over and electrically isolated from the floating gate.

2. The memory cell according to claim 1 , wherein the interconnect structure comprises interconnect layers of line features stacked upon one another, and further comprises via layers of via features interconnecting the line features between the interconnect layers.

3. The memory cell according to claim 2 , wherein the shield comprises one of the line features that directly overlies the floating gate.

4. The memory cell according to claim 2 , wherein the shield comprises one of the via features that directly overlies the floating gate.

5. The memory cell according to claim 2 , wherein the floating gate is continuous, and wherein the shield comprises:
a first line feature of the interconnect layers that individually covers a first subset of the floating gate at a first height above the floating gate; and
a second line feature of the interconnect layer that individually covers a second subset of the floating gate at a second height above the floating gate, wherein the first and second heights are different, and wherein the first and second subsets are different.

6. The memory cell according to claim 5 , wherein the first and second line features collectively cover about 100% of the floating gate.

7. The memory cell according to claim 2 , wherein the shield comprises:
a line feature of the interconnect layers arranged directly over the floating gate; and
a via feature of the via layers arranged directly over the floating gate.

8. The memory cell according to claim 2 , wherein the interconnect or via layers are limited to a periphery of the memory cell, except for a portion for the interconnect or via layers making up the shield, when the interconnect structure is viewed in profile, and wherein each of the via layers extends from contact with an underlying one of the interconnect layers to contact with an overlying one of the interconnect layers.

9. The memory cell according to claim 2 , wherein the interconnect and via layers are limited to a periphery of the memory cell, except for a portion for the interconnect and via layers making up the shield, when the interconnect structure is viewed in profile.

10. The memory cell according to claim 1 , wherein a footprint size of the shield is less than or equal to that of the floating gate.

11. The memory cell according to claim 1 , wherein the shield comprises a plurality of conductive features of the interconnect structure that individually cover at least a portion of the floating gate, and wherein the conductive features are distributed amongst a plurality of heights above the floating gate.

12. The memory cell according to claim 1 , wherein an upper surface of the semiconductor substrate comprises dangling bonds terminated by hydrogen ions.

13. The memory cell according to claim 1 , wherein the transistors comprise a select gate laterally spaced over the semiconductor substrate from the floating gate, wherein the transistors share a common source/drain region arranged between the select and floating gate, and wherein the transistors comprise individual source/drain regions on opposite sides of the select and floating gates as the common source/drain region.

14. A memory cell with floating gate shielding, comprising:
a pair of transistors arranged on a semiconductor substrate and electrically coupled in series, wherein the transistors comprise a floating gate configured to store a bit of data;
an interconnect structure overlying the transistors, wherein the interconnect structure comprises interconnect layers of line features stacked upon one another, and further comprises via layers of via features interconnecting the line features between the interconnect layers;
a shield arranged directly over the floating gate and comprising a feature of the interconnect or via layers; and
a diffusion path for hydrogen ions extending from a top surface of the interconnect structure to the shield, wherein the diffusion path is line shaped and substantially orthogonal to a top surface of the floating gate, and wherein the shield is configured to block hydrogen diffusing along the diffusion path from reaching the floating gate.

15. The memory cell according to claim 14 , wherein the shield comprises a plurality of via features distributed amongst several of the via layers, and wherein the via features of the plurality each partially covers the floating gates.

16. The memory cell according to claim 14 , wherein the interconnect structure further comprises an interlayer dielectric (ILD) layer within which the interconnect layers and the via layers are stacked, wherein the shield comprises a line feature of the interconnect layers and a via feature of the via layers, and wherein the via feature extends from contact with the line feature to contact with the ILD layer at a horizontal surface of the via feature.

17. The memory cell according to claim 14 , wherein the transistors further comprise a select gate adjacent to the floating gate, and wherein the memory cell further comprises:
a second diffusion path for hydrogen ions extending in parallel with the diffusion path, from the top surface of the interconnect structure to the select gate, wherein the second diffusion path is line shaped and unimpeded by the interconnect layers and the via layers.

18. The memory cell according to claim 14 , where the semiconductor substrate comprises dangling bonds terminated by hydrogen, and wherein the shield comprises hydrogen absorbed from a surrounding environment.

19. The memory cell according to claim 14 , wherein the transistors comprise a source/drain region bordering the floating gate, wherein the interconnect layers comprise a first wiring layer spaced over the floating gate, wherein the via layers comprise a first via layer extending from contact with the first via layer to contact with the source/drain region, and wherein the shield comprises a line feature that is in the first wiring layer and that is directly over the floating gate.

20. A one-time programmable memory cell comprising:
a semiconductor substrate comprising a first source/drain region, a second source/drain region, and a third source/drain region, wherein the second source/drain region is between the first and second source/drain regions, and wherein dangling bonds along a top surface of the semiconductor substrate are terminated by hydrogen;
a select transistor comprising the first and second source/drain regions, and further comprising a select gate electrode, wherein the select gate electrode is over the semiconductor substrate, and wherein the selec

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hung-Lin
• Cheng Shyh-Wei
• Chu Che-Jung

Classifications

• G11C16/0433 Primary

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• H01L27/11521 Primary

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• G11C17/08

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title