Methods and apparatus for integrated circuit failsafe fuse package with arc arrest

Patent metadata

Field	Value
Publication number	US-9865537-B1
Application number	US-201615395817-A
Country	US
Kind code	B1
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

In described examples, an apparatus includes: an integrated circuit die having multiple terminals; the integrated circuit die positioned on a die pad portion of a leadframe having leads for external connections, at least some of the leads having an inner portion electrically coupled to at least one terminal of the integrated circuit die; a fuse element coupled between one of the leads of the leadframe and at least one terminal selected from the multiple terminals of the integrated circuit die; and encapsulation material surrounding the integrated circuit die and the leadframe to form a packaged integrated circuit including the integrated circuit die and the fuse element, and having a cavity in the encapsulation material surrounding the fuse element such that the fuse element is spaced from the encapsulation material.

First claim

What is claimed is:

1. An apparatus, comprising:
an integrated circuit die having multiple terminals;
a leadframe having a die pad portion, the integrated circuit die positioned on and attached to the die pad portion;
the leadframe having leads for external connections, at least some of the leads having an inner portion electrically coupled to at least one terminal selected from the multiple terminals of the integrated circuit die;
a fuse element coupled between one of the leads of the leadframe and at least one terminal selected from the multiple terminals of the integrated circuit die; and
encapsulation material surrounding the integrated circuit die and the leadframe to form a packaged integrated circuit including the integrated circuit die and the fuse element, and having a cavity in the encapsulation material surrounding the fuse element such that the fuse element is spaced from the encapsulation material.

2. The apparatus of claim 1 , in which the cavity is a void in the encapsulation material surrounding the fuse element.

3. The apparatus of claim 2 , and further including a vent extending from the cavity to an external surface of the encapsulation material.

4. The apparatus of claim 3 , and further including a cover material covering the vent at an exterior surface of the encapsulation material.

5. The apparatus of claim 4 , in which the cover material is arranged to blow away from the vent in response to gas pressure in the cavity.

6. The apparatus of claim 1 , in which the cavity includes a sublimatable sacrificial encapsulant material (SSEM) surrounding the fuse element.

7. The apparatus of claim 1 , in which the fuse element is a fusible link to form an open circuit in an overcurrent condition.

8. The apparatus of claim 1 , in which the fuse element is a bond wire to form an open circuit in an overcurrent condition.

9. The apparatus of claim 1 , in which the fuse element is formed by a first portion of a metal clip having a first thickness, a second portion of the metal clip having a second thickness greater than the first thickness.

10. The apparatus of claim 1 , in which the fuse element is a wire of a first diameter, coupled to bond wire portions of a second diameter that is greater than the first diameter.

11. The apparatus of claim 1 , in which the integrated circuit die includes a transistor and the fuse element is coupled in series between a terminal of the integrated circuit die and a lead of the leadframe.

12. The apparatus of claim 1 , in which the fuse element is configured to heat up and burn during an overcurrent event, and the fuse element is to subsequently form an open circuit.

13. A power integrated circuit with overcurrent protection, comprising:
an integrated circuit die including a FET disposed on a portion of a leadframe and having a source terminal, a gate terminal, and a drain terminal;
bond wires coupling external terminals of the leadframe to at least one of the source, drain and gate terminals of the integrated circuit die;
a fuse element coupled in series between an external terminal of the leadframe and at least one of the source terminal and the drain terminal of the integrated circuit die;
encapsulation material surrounding the integrated circuit die and the leadframe to form a packaged integrated circuit, the encapsulation material being spaced from the fuse element by a cavity in the encapsulation material, the fuse element being surrounded by the cavity; and
a vent extending from an exterior surface of the packaged integrated circuit to the cavity and being covered by a vent cover material configured to blow off the vent in response to pressure in the cavity.

14. The power integrated circuit of claim 13 , in which the cavity includes a void containing air.

15. The power integrated circuit of claim 13 , in which the cavity includes sacrificial sublimatable encapsulation material (SSEM) surrounding the fuse element.

Assignees

• Texas Instruments Inc

Inventors

• Male Barry Jon
• Kummerl Steve
• Cook Benjamin Stassen

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/124

  the encapsulations having cavities other than that occupied by chips · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W70/464

  Additional interconnections in combination with leadframes · CPC title