Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component

Patent metadata

Field	Value
Publication number	US-9865482-B2
Application number	US-201213438696-A
Country	US
Kind code	B2
Filing date	Apr 3, 2012
Priority date	Sep 9, 2008
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.

First claim

What is claimed:

1. A semiconductor device, comprising:
a substrate;
a conductive via formed through the substrate;
an integrated passive device (IPD) structure including a first IPD formed directly over the conductive via and the substrate and electrically connected to the conductive via, the conductive via disposed within a footprint of the first IPD;
an encapsulant deposited over a side surface of the substrate and the IPD structure;
a first interconnect structure formed over the IPD structure and the encapsulant and electrically connected to the IPD structure; and
a discrete semiconductor component disposed within the encapsulant outside a footprint of the substrate, wherein the discrete semiconductor component includes a capacitor comprising a capacitance value over 100 picofarads (pF).

2. The semiconductor device of claim 1 , further including a second interconnect structure formed over the substrate and the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the conductive via.

3. The semiconductor device of claim 2 , wherein the second interconnect structure includes a second IPD.

4. The semiconductor device of claim 1 , wherein the first IPD includes a capacitor or inductor.

5. The semiconductor device of claim 1 , wherein the first interconnect structure includes a second IPD.

6. A semiconductor device, comprising:
an integrated passive device (IPD) structure including,
(a) a substrate,
(b) a first IPD formed over a surface of the substrate, and
(c) a second IPD formed over the surface of the substrate;

a third IPD formed over the IPD structure opposite the surface of the substrate;
an encapsulant deposited around the IPD structure;
a first insulating layer formed over the encapsulant and third IPD; and
an interconnect structure formed over the IPD structure and the encapsulant and electrically connected to the IPD structure, wherein the interconnect structure includes:
(d) a second insulating layer formed over the IPD structure and the encapsulant, and
(e) a first conductive layer formed over the IPD structure and the encapsulant and the first IPD includes a portion of the first conductive layer of the interconnect structure.

7. The semiconductor device of claim 6 , further including a conductive via formed through the substrate.

8. The semiconductor device of claim 6 , wherein the first IPD includes:
a second conductive layer formed over the surface of the substrate;
a third insulating layer formed over the second conductive layer; and
a third conductive layer formed over the third insulating layer.

9. The semiconductor device of claim 6 , wherein the third IPD includes a second conductive layer formed as an inductor.

10. The semiconductor device of claim 6 , further including a discrete semiconductor component disposed within the encapsulant around the IPD structure.

11. A semiconductor device, comprising:
an integrated passive device (IPD) structure including,
(a) a substrate,
(b) a first IPD formed over a surface of the substrate, and
(c) a second IPD formed over the surface of the substrate;

a first conductive layer formed over the IPD structure as an inductor;
an encapsulant deposited around the IPD structure;
a first insulating layer formed over the encapsulant and IPD structure; and
an interconnect structure formed over the IPD structure and the encapsulant, wherein the interconnect structure includes:
(d) a second insulating layer formed over the IPD structure and the encapsulant, and
(e) a second conductive layer formed over the IPD structure and the encapsulant and the first IPD includes a portion of the second conductive layer of the interconnect structure.

12. The semiconductor device of claim 11 , further including a conductive via formed through the substrate.

13. The semiconductor device of claim 11 , wherein the first IPD includes:
a third conductive layer formed over the surface of the substrate;
a third insulating layer formed over the third conductive layer; and
a fourth conductive layer formed over the third insulating layer.

14. The semiconductor device of claim 11 , further including a discrete semiconductor component disposed within the encapsulant around the IPD structure.

15. A semiconductor device, comprising:
an integrated passive device (IPD) structure including,
(a) a substrate,
(b) a first IPD formed over a surface of the substrate, and
(c) a second IPD formed over the surface of the substrate;

a first conductive layer over the IPD structure, wherein a first portion of the first conductive layer is formed as an inductor and the first IPD includes a second portion of the first conductive layer;
an encapsulant deposited around the IPD structure; and
an interconnect structure formed over the IPD structure and the encapsulant.

16. The semiconductor device of claim 15 , further including a conductive via formed through the substrate.

17. The semiconductor device of claim 15 , wherein the first IPD includes:
a second conductive layer formed over the surface of the substrate;
an insulating layer formed over the second conductive layer; and
the second portion of the first conductive layer formed over the insulating layer.

18. The semiconductor device of claim 15 , further including an insulating layer formed over the encapsulant and IPD structure.

19. The semiconductor device of claim 15 , further including a discrete semiconductor component disposed within the encapsulant around the IPD structure.

20. The semiconductor device of claim 15 , wherein the interconnect structure includes:
an insulating layer formed over the IPD structure and the encapsulant; and
a second conductive layer formed over the IPD structure and the encapsulant.

Assignees

• Lin Yaojian
• Fang Jianmin
• Chen Kang
• Cao Haijing
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Fang Jianmin
• Chen Kang
• Cao Haijing

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title