Recess filling method and processing apparatus

Patent metadata

Field	Value
Publication number	US-9865467-B2
Application number	US-201514919381-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Oct 29, 2014
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess.

First claim

What is claimed is:

1. A method of filling a recess of a workpiece, the workpiece having a semiconductor substrate and an insulating film formed on the semiconductor substrate, the recess penetrating the insulating film and extending to an inside of the semiconductor substrate, the method comprising:
forming a first thin film made of a semiconductor material along a wall surface defining the recess in the semiconductor substrate;
annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess in the semiconductor substrate, without moving the first thin film;
forming a second thin film made of the semiconductor material along the wall surface defining the recess; and
annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess.

2. The method of claim 1 , wherein the first pressure is higher than 133.3 Pa, and the second pressure is equal to or lower than 133.3 Pa.

3. The method of claim 1 , further comprising: between forming an epitaxial region and forming a second thin film, etching the first thin film.

4. The method of claim 1 , further comprising: after forming a further epitaxial region, etching the second thin film.

5. The method of claim 1 , further comprising: before forming at least one of the first thin film and the second thin film, forming a liner layer that is an amorphous semiconductor layer.

6. The method of claim 5 , further comprising: before forming the liner layer, forming a seed layer using an aminosilane-based gas or a high-order silane gas.

Assignees

• Tokyo Electron Ltd

Inventors

• Suzuki Daisuke
• Chiba Youichirou
• Yamada Takumi

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title