Apparatuses and methods for implementing masked write commands

Patent metadata

Field	Value
Publication number	US-9508409-B2
Application number	US-201414254378-A
Country	US
Kind code	B2
Filing date	Apr 16, 2014
Priority date	Apr 16, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory bank;
a local buffer circuit associated with the memory bank; and
an address control circuit coupled to the memory bank and configured to receive a command and an address associated with the command, the address control circuit comprising:
a latency circuit configured to receive the command and to assert a first control signal and a second control signal responsive to receipt of the command; and
a global buffer circuit configured to store the address, the address control circuit configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency, the global buffer circuit configured to store the address responsive to the first control signal being asserted, the global buffer circuit configured to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein, and
wherein the local buffer circuit is configured to store the address in the local buffer circuit responsive to the second control signal being asserted.

2. The apparatus of claim 1 , wherein during an operation associated with the command, the address control circuit is further configured to assert the first control signal if the operation is a masked write operation and to assert the second control signal if the operation is a write operation.

3. The apparatus of claim 1 , wherein the address control circuit is further configured to delay the command using the one of the plurality of command paths based on a type of the command.

4. The apparatus of claim 1 ,
wherein the global buffer circuit is coupled to the latency circuit and configured to receive the address and the first control signal.

5. The apparatus of claim 4 , wherein the address control circuit is further configured to assert the second control signal responsive to receipt of the command, and wherein the local buffer circuit associated with the memory bank is configured to receive the second control signal.

6. The apparatus of claim 1 , wherein the command is a masked write command.

7. An apparatus, comprising:
an address control circuit comprising:
a latency circuit configured to receive a command and to assert a first control signal and a second control signal responsive to receipt of the command; and
a global buffer circuit coupled to the latency circuit and configured to receive the first control signal and an address associated with the command, the global buffer circuit configured to store the address responsive to the latency circuit asserting the first control signal; and

a local buffer circuit coupled to the latency circuit and the global buffer circuit, the local buffer circuit associated with a memory bank and configured to receive the second control signal and the address and configured to store the address responsive to the latency circuit asserting the second control signal.

8. The apparatus of claim 7 , wherein the address is a first address and wherein the global buffer circuit is configured to provide the first address responsive to storing the first address, the global buffer circuit further configured to receive the second control signal and to provide a second address responsive to the second control signal no longer being asserted.

9. The apparatus of claim 8 , wherein the latency circuit is further configured to receive the address and to assert the second control signal based on the address.

10. The apparatus of claim 8 , wherein the local buffer circuit is further configured to automatically provide the address to a local column address bus when no other addresses are stored in the local buffer circuit.

11. The apparatus of claim 8 , wherein the local buffer circuit is a first local buffer circuit and the address is a first address, the apparatus further comprising:
a second local buffer circuit coupled to the latency circuit and the global buffer circuit and configured to store a second address responsive to the latency circuit asserting a third control signal.

12. The apparatus of claim 8 , wherein the command is a masked write command.

13. The apparatus of claim 8 , wherein the apparatus is included in a memory.

14. An apparatus, comprising:
an address control circuit configured to receive a write command and a masked write command for a memory bank of the plurality of memory banks, the write command provided to the address control circuit before the masked write command, and the address control circuit configured to receive an address associated with each of the commands and indicative of the memory bank of a plurality of memory banks, the address control circuit further configured to provide the address to a local buffer circuit associated with the memory bank of the plurality of memory banks and to assert a first control signal associated with the memory bank of the plurality of memory banks prior to a write operation associated with the write command being performed and to assert a second control signal during the write operation associated with the write command,
wherein the local buffer circuit provides the address as a local address responsive to the first control signal being asserted and provides a new address as the local address responsive to the second control signal no longer being asserted, and
wherein the address control circuit is configured to delay the masked write command such that a write operation associated with the write command is performed prior to a read operation associated with the masked write command.

15. The apparatus of claim 14 , wherein the local buffer associated with the memory bank of the plurality of memory banks is configured to store the address responsive to the first control signal being asserted.

16. The apparatus of claim 14 , wherein the address control circuit is further configured to provide the address a number of clock cycles after receiving the write command.

17. The apparatus of claim 14 , wherein the address control circuit includes a global buffer circuit configured to store addresses associated with respective write and masked write commands and for the plurality of memory banks.

18. The apparatus of claim 14 , wherein the address control circuit is further configured to provide the address to the memory bank of the plurality of memory banks responsive to receipt of the address when the address control circuit is not storing any other addresses.

19. The apparatus of claim 14 , wherein the address control circuit is configured to store the address in a FIFO buffer.

20. An apparatus, comprising:
an address control circuit configured to receive a write command associated with a memory bank and a masked write command associated with the memory bank, the write command provided to the address control circuit before the masked write command, and the address control circuit configured to delay the write command a first amount using a first command path and to delay the masked write command a second amount using a second command path, the address control circuit further configured to assert a control signal of a first plurality of control signals during an operation associated with the write command and to assert a control signal of a second plurality of control signals during an operation associated with the masked write command,
wherein each control signal of the first plurality of control signals is associated with a respective memory bank of a plurality of memory banks and wherein each control signal of the second plurality of control signals is associated with a r

Assignees

• Micron Technology Inc

Inventors

• Hadrick Mark K
• Wright Jeffrey P
• Wong Victor
• Lovett Simon J
• Morgan Donald M
• Jones William F
• Ayyapureddi Sujeet
• Gans Dean D
• Kwak Jongtae

Classifications

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C7/1009

  Data masking during input/output · CPC title

• G11C7/1042

  using interleaving techniques, i.e. read-write of one part of the memory while preparing another part · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C2207/229

  Timing of a write operation · CPC title