Optimal sampling of data-bus signals using configurable individual time delays

Patent metadata

Field	Value
Publication number	US-9864713-B2
Application number	US-201514957617-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Dec 5, 2014
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.

First claim

The invention claimed is:

1. A method, comprising:
receiving a group of logic signals to be sampled at a common sampling timing;
selecting for the logic signals in the group respective individual time delays, which individually align each of the logic signals to the common sampling timing, by:
identifying for each logic signal a respective timing window during which the logic signal is valid; and
choosing the common sampling timing and the individual time delays such that the timing windows overlap the common sampling timing;

delaying each of the logic signals by the respective selected individual time delay; and
sampling the entire group of the delayed logic signals at the common sampling timing.

2. The method according to claim 1 , wherein selecting the individual time delays comprises centering each of the timing windows on the common sampling timing.

3. The method according to claim 1 , wherein selecting the individual time delays comprises, in response to detecting that it is impossible to center all the timing windows on the common sampling timing, choosing the common sampling timing and the individual time delays such that the common sampling timing is separated from edges of the timing windows by at least a predefined time margin.

4. The method according to claim 1 , wherein delaying the logic signals is performed by configurable delay elements having a finite delay range, and wherein selecting the individual time delays comprises ascertaining that the individual time delays are all within the finite delay range.

5. The method according to claim 1 , wherein receiving the logic signals comprises receiving data (DQ) signals from a memory device.

6. The method according to claim 5 , wherein receiving the logic signals comprises receiving at least one data strobe (DQS) signal from the memory device.

7. A method, comprising:
receiving a group of logic signals to be sampled at a common sampling timing;
selecting for the logic signals in the group respective individual time delays, which individually align each of the logic signals to the common sampling timing, by:
identifying, for a set of possible supply voltages, respective timing windows during which at least a predefined number of the logic signals are valid; and
setting the individual time delays so as to position the common sampling timing at a centroid of a two-dimensional region formed by the timing windows in a voltage-timing plane;

delaying each of the logic signals by the respective selected individual time delay; and
sampling the entire group of the delayed logic signals at the common sampling timing.

8. Apparatus, comprising:
a calibrator, configured to:
receive a group of logic signals to be sampled at a common sampling timing;
select for the logic signals in the group respective individual time delays that individually align each of the logic signals to the common sampling timing, by (i) identifying for each logic signal a respective timing window during which the logic signal is valid, and (ii) choosing the common sampling timing and the individual time delays such that the timing windows overlap the common sampling timing; and
delay each of the logic signals by the respective selected individual time delay; and

a sampler, configured to sample the entire group of the delayed logic signals at the common sampling timing.

9. The apparatus according to claim 8 , wherein the calibrator is configured to select the individual time delays so as to center each of the timing windows on the common sampling timing.

10. The apparatus according to claim 8 , wherein, in response to detecting that it is impossible to center all the timing windows on the common sampling timing, the calibrator is configured to choose the common sampling timing and the individual time delays such that the common sampling timing is separated from edges of the timing windows by at least a predefined time margin.

11. The apparatus according to claim 8 , wherein the calibrator comprises configurable delay elements that are configured to delay the logic signals and have a finite delay range, and wherein the calibrator is configured to ascertain that the individual time delays are all within the finite delay range.

12. The apparatus according to claim 8 , wherein the logic signals comprise data (DQ) signals received from a memory device.

13. The apparatus according to claim 12 , wherein the logic signals comprise at least one data strobe (DQS) signal from the memory device.

14. Apparatus, comprising:
a calibrator, configured to:
receive a group of logic signals to be sampled at a common sampling timing;
select for the logic signals in the group respective individual time delays that individually align each of the logic signals to the common sampling timing, by:
identifying, for a set of possible supply voltages, respective timing windows during which at least a predefined number of the logic signals are valid; and
setting the individual time delays so as to position the common sampling timing at a centroid of a two-dimensional region formed by the timing windows in a voltage-timing plane; and

delay each of the logic signals by the respective selected individual time delay; and

a sampler, configured to sample the entire group of the delayed logic signals at the common sampling timing.

Assignees

• Marvell Israel (M I S L) Ltd
• Marvell Israel (M I S L ) Ltd

Inventors

• Benjamin Ofer
• Bar-Lev Eldad

Classifications

• G06F13/4054

  where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus · CPC title

• G06F13/4031

  with arbitration · CPC title

• G06F13/3625 Primary

  using a time dependent access · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title