Calibration in a control device receiving from a source synchronous interface

Patent metadata

Field	Value
Publication number	US-2016133305-A1
Application number	US-201414534487-A
Country	US
Kind code	A1
Filing date	Nov 6, 2014
Priority date	Nov 6, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.

First claim

1 . A control device for receiving from a source synchronous interface having a data bus and a source clock, the control device comprising:
a data path comprising a data delay unit coupled to a data input of a sampling circuit; a clock path comprising a clock delay unit coupled to a clock input of the sampling circuit; a multiplexing circuit operable to selectively couple a reference clock or the data bus to an input of the data delay unit, and selectively couple the reference clock or the source clock to an input of the clock delay unit; and a calibration unit coupled to a data output of the sampling circuit, the calibration unit operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.

2 . The control device of claim 1 , wherein the calibration unit is operable to control the multiplexing circuit to couple the reference clock to the inputs of both of the data delay unit and the clock delay unit in a first mode, and couple the data bus to the input of the data delay unit and the source clock to the input of the clock delay unit in a second mode.

3 . The control device of claim 2 , wherein, while in the first mode, the calibration unit adjusts delay values of the data delay unit and the clock delay unit to align signals on the data path and the clock path and shift the output of the clock delay unit by 90 degrees.

4 . The control device of claim 2 , wherein, while in the first mode, the calibration unit adjusts delay values of the data delay unit and the clock delay unit to align signals on the data path and the clock path, and wherein, while in the second mode, the calibration unit adjusts the delay values of the data delay unit and the clock delay unit to center the source clock in a data eye of the data bus.

5 . The control device of claim 2 , wherein the data bus comprises a plurality of data signals, and wherein the data delay unit comprises a plurality of digital delay lines associated with the respective plurality of data signals.

6 . The control device of claim 5 , wherein, while in the first mode, the calibration unit adjusts tap values of the plurality of digital delay lines to align the plurality of data signals.

7 . The control device of claim 1 , further comprising:
a master delay unit having an input coupled to receive the reference clock; and a flip-flop coupled to sample the reference clock according to output of the master delay unit; wherein the calibration unit is coupled to a data output of the flip-flop, and the calibration unit is operable to align the output of the master delay unit and the reference clock, establish a master relative delay between the output of the master delay unit and the reference clock, and adjust a delay value of the master delay unit to maintain the master relative delay.

8 . The control device of claim 7 , wherein the calibration unit is operable to maintain the relative delay between the data path and the clock path by adjusting delay values of the data delay unit and the clock delay unit to maintain ratios of the delay value of the master delay unit to the delay values of the data delay unit and the clock delay unit.

9 . The control device of claim 7 , further comprising:
a fixed delay circuit having an input coupled to receive the reference clock and an output coupled to a data input of the flip-flop.

10 . The control device of claim 1 , wherein the source synchronous interface comprises a synchronous dynamic random access memory (SDRAM) interface, and wherein the control device is disposed in an integrated circuit (IC) coupled to an SDRAM system having the SDRAM interface.

11 . A system, comprising:
a synchronous dynamic random access memory (SDRAM) system having a data bus and a source clock; and a memory control device coupled to the SDRAM system, the memory control device including:
a sampling circuit;
a data delay unit coupled to a data input of the sampling circuit;
a clock delay unit coupled to a clock input of the sampling circuit;
a multiplexing circuit operable to selectively couple a reference clock or the data bus to an input of the data delay unit, and selectively couple the reference clock or the source clock to an input of the clock delay unit; and
a calibration unit coupled to a data output of the sampling circuit, the calibration unit operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between outputs of the data delay unit and the clock delay unit.

12 . The system of claim 11 , wherein the calibration unit is operable to control the multiplexing circuit to couple the reference clock to the inputs of both the data delay unit and the clock delay unit in a first mode and, while in the first mode, adjust delay values of the data delay unit and the clock delay unit to align outputs of the data delay unit and the clock delay unit and shift the output of the clock delay unit by 90 degrees.

13 . The system of claim 12 , wherein the calibration unit is operable to control the multiplexing circuit to couple the reference clock to the inputs of both the data delay unit and the clock delay unit in a first mode and, while in the first mode, adjust delay values of the data delay unit and the clock delay unit for signal alignment, and wherein the calibration unit is operable to control the multiplexing circuit to couple the data bus to the input of the data delay unit and the source clock to the input of the clock delay unit in a second mode and, while in the second mode, adjust the delay values of the data delay unit and the clock delay unit to center the source clock in a data eye of the data bus.

14 . The system of claim 12 , wherein the data bus comprises a plurality of data signals, wherein the data delay unit comprises a plurality of digital delay lines associated with the respective plurality of data signals, and wherein, while in the first mode, the calibration unit is operable to adjust tap values of the plurality of digital delay lines to align the plurality of data signals.

15 . The system of claim 11 , wherein the memory control device further comprises:
a master delay unit having an input coupled to receive the reference clock; and a flip-flop coupled to sample the reference clock according to output of the master delay unit; wherein the calibration unit is coupled to a data output of the flip-flop, and the calibration unit is operable to:
align the output of the master delay unit and the reference clock;
establish a master relative delay between the output of the master delay unit and the reference clock and adjust a delay value of the master delay unit to maintain the master relative delay; and
maintain the relative delay between the data path and the clock path by adjusting delay values of the data delay unit and the clock delay unit to maintain ratios of the delay value of the master delay unit to the delay values of the data delay unit and the clock delay unit.

16 . A method of receiving from a source synchronous interface having a data bus and a source clock, the method comprising:
coupling a reference clock to a data path and a clock path, the data path including a data delay unit coupled to a data input of a sampling circuit, the clock path including a clock delay unit coupled to a clock input of the sampling circuit; controlling the data delay unit and the clock delay unit to establish a relative delay between the d

Assignees

• Xilinx Inc

Inventors

• Magee Terence J
• Zhang Xiaoqian

Classifications

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G06F13/4243 Primary

  with synchronous protocol · CPC title