Silicon photonic chip with through VIAS

Patent metadata

Field	Value
Publication number	US-9864133-B2
Application number	US-201615208658-A
Country	US
Kind code	B2
Filing date	Jul 13, 2016
Priority date	Nov 13, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.

First claim

We claim:

1. A photonic chip comprising:
a first substrate, comprising:
a crystalline semiconductor substrate, and
a through silicon via (TSV) extending through the crystalline semiconductor substrate;

a second substrate bonded to the first substrate at a wafer bonding interface, the second substrate, comprising:
an active surface layer comprising an optical component optically coupled to a semiconductor waveguide;
a through oxide via (TOV) formed in both the first and second substrates, wherein the TOV crosses the wafer bonding interface and is electrically coupled to the TSV, wherein a first end of the TSV is coupled to a metal layer in the first substrate and a second end of the TSV is exposed on a first external surface, and wherein a first end of the TOV is coupled to the metal layer in the first substrate and a second end of the TOV is exposed on a second external surface opposite the first external surface;
an evanescent coupler spaced apart from the semiconductor waveguide along a direction normal to the active surface layer, wherein the evanescent coupler is optically coupled to the semiconductor waveguide; and
an optical interface optically coupled to the evanescent coupler, wherein the optical interface permits optical signals to be transferred between the photonic chip and an external optical device via a coupling surface.

2. The photonic chip of claim 1 , wherein a first end of the TSV is coupled to a metal layer in the first substrate and a second end of the TSV is exposed on an external surface of the semiconductor substrate, and wherein a first end of the TOV is coupled to the metal layer in the first substrate and a second end of the TOV is electrically coupled to the optical component.

3. The photonic chip of claim 2 , wherein the TOV and TSV provide an electrical path for transmitting data signals for controlling the optical component, wherein the optical component is one of an optical modulator and an optical detector.

4. The photonic chip of claim 1 , wherein a first end of the TSV is coupled to a metal layer in the first substrate and a second end of the TSV is exposed on a first external surface, and wherein a first end of the TOV is coupled to the metal layer in the first substrate and a second end of the TOV is exposed on a second external surface opposite the first external surface.

5. The photonic chip of claim 1 , wherein the wafer bonding interface comprises an oxide-oxide bond between insulative material in the first and second substrates.

6. The photonic chip of claim 1 , wherein at least a portion of the optical interface is disposed in the first substrate.

7. The photonic chip of claim 6 , wherein evanescent coupler is disposed in the first substrate, wherein the optical interface and the evanescent coupler comprises respective waveguides formed from at least one of silicon nitride and silicon oxynitride.

8. The photonic chip of claim 6 , wherein the optical interface comprises at least four waveguides, wherein each of the four waveguides change width as the four waveguides extend away from the coupling surface.

9. The photonic chip of claim 1 , wherein the optical interface comprises a plurality of waveguides forming a grating structure, wherein each of the plurality of waveguides is spaced apart from a neighboring waveguide.

10. The photonic chip of claim 1 , wherein the optical interface comprises a subwavelength grating that permits edge coupling.

Assignees

• Cisco Tech Inc
• Cisco Tech Inc

Inventors

• Patel Vipulkumar
• Webster Mark
• Tummidi Ravi
• Nadeau Mary

Classifications

• G02B6/124

  Geodesic lenses or integrated gratings · CPC title

• G02B6/1228

  Tapered waveguides, e.g. integrated spot-size transformers (for coupling with fibres G02B6/305) · CPC title

• G02B6/305

  and having an integrated mode-size expanding section, e.g. tapered waveguide · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title

• G02B6/34

  utilising prism or grating {(G02B6/293 takes precedence)} · CPC title