Selective area heating for 3D chip stack

Patent metadata

Field	Value
Publication number	US-9860996-B2
Application number	US-201615214535-A
Country	US
Kind code	B2
Filing date	Jul 20, 2016
Priority date	Mar 7, 2013
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

First claim

What is claimed is:

1. A method of forming a 3D package comprising a laminate chip carrier, an interposer, and a top chip, the method comprising:
attaching a first plurality of solder bumps of the laminate chip carrier to a first plurality of metallic contacts of the interposer by applying a first selective non-uniform heat, a first selective non-uniform cooling, and a first uniform pressure to the first plurality of solder bumps, resulting in solid state diffusion of the first plurality of solder bumps into the first plurality of metallic contacts of the interposer, wherein the first selective non-uniform heat is a temperature less than the reflow temperature of the first plurality of solder bumps; and
attaching a second plurality of solder bumps of the interposer to a second plurality of metallic contacts of the top chip by applying a second selective non-uniform heat and a second uniform pressure to the second plurality of solder bumps, resulting in solid state diffusion of the second plurality of solder bumps into the second plurality of metallic contacts of the top chip, wherein the second selective non-uniform heat is a temperature less than the reflow temperature of the second plurality of solder bumps.

2. The method of claim 1 , wherein at least one of the laminate chip carrier, the interposer, or the top chip comprises a height variation defined as a maximum deviation from a horizontal flat surface.

3. The method of claim 1 , wherein attaching the first plurality of solder bumps of the laminate chip carrier to the first plurality of metallic contacts of the interposer comprises:
applying the first selective non-uniform heat to a top surface of the interposer, a bottom surface of the laminate chip carrier, or both.

4. The method of claim 1 , wherein attaching the second plurality of solder bumps of the interposer to the second plurality of metallic contacts of the top chip comprises:
applying the second selective non-uniform heat to a top surface of the top chip, a bottom surface of the laminate chip carrier, or both.

5. The method of claim 1 , further comprising:
placing the 3D package on a fixture such that the laminate chip carrier is in direct contact with the fixture, the fixture comprising ceramic, aluminum, or copper.

6. The method of claim 1 , further comprising:
using a reflow oven with a controlled time-temperature profile.

7. The method of claim 1 , further comprising:
underfilling a first space between the laminate chip carrier and the interposer around the first plurality of solder bumps; and
underfilling a second space between the interposer and the top chip around the second plurality of solder bumps.

8. A method of forming a 3D package comprising a laminate chip carrier, an interposer, and a top chip, the method comprising:
attaching a first plurality of solder bumps of the laminate chip carrier to a first plurality of metallic contacts of the interposer by applying a first selective non-uniform heat, a first selective non-uniform cooling, and a first uniform pressure to the first plurality of solder bumps, resulting in solid state diffusion of the first plurality of solder bumps into the first plurality of metallic contacts of the interposer, wherein the first selective non-uniform heat is a temperature less than the reflow temperature of the first plurality of solder bumps; and
attaching a second plurality of solder bumps of the interposer to a second plurality of metallic contacts of the top chip by applying a second selective non-uniform heat, a second selective non-uniform cooling, and a second uniform pressure to the second plurality of solder bumps, resulting in solid state diffusion of the second plurality of solder bumps into the second plurality of metallic contacts of the top chip, wherein the second selective non-uniform heat is a temperature less than the reflow temperature of the second plurality of solder bumps.

9. The method of claim 8 , wherein attaching the first plurality of solder bumps of the laminate chip carrier to the first plurality of metallic contacts of the interposer comprises:
applying the first selective non-uniform heat to a top surface of the interposer, a bottom surface of the laminate chip carrier, or both.

10. The method of claim 8 , wherein attaching the second plurality of solder bumps of the interposer to the second plurality of metallic contacts of the top chip comprises:
applying the second selective non-uniform heat to a top surface of the top chip, a bottom surface of the laminate chip carrier, or both.

11. The method of claim 8 , further comprising:
placing the 3D package on a fixture such that the laminate chip carrier is in direct contact with the fixture, the fixture comprising ceramic, aluminum, or copper.

12. The method of claim 8 , further comprising:
underfilling a first space between the laminate chip carrier and the interposer around the first plurality of solder bumps; and
underfilling a second space between the interposer and the top chip around the second plurality of solder bumps.

Assignees

• IBM

Inventors

• Interrante Mario J
• Sakuma Katsuyuki

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07234

  Using a reflow oven · CPC title

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title