Structure to reduce chip shift during assembly
US-2024395758-A1 · Nov 28, 2024 · US
Selective area heating for 3D chip stack
US9105629B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105629-B2 |
| Application number | US-201313787913-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 7, 2013 |
| Priority date | Mar 7, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A method of forming a 3D package including joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat, a first selective non-uniform cooling, and first uniform pressure, joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure, heating the 3D package and the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where a temperature of the first and second selective non-uniform heat is less than the reflow temperature of the first and second pluralities of solder bumps, respectively.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a 3D package comprising a laminate chip carrier, an interposer, and a top chip, the method comprising: attaching a first plurality of solder bumps of the laminate chip carrier to a first plurality of metallic contacts of the interposer by applying a first selective non-uniform heat, a first selective non-uniform cooling, and a first uniform pressure to the first plurality of solder bumps, resulting in solid state diffusion of the first pl…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105629B2 cover?
- A method of forming a 3D package including joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat, a first selective non-uniform cooling, and first uniform pressure, joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a se…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10W95/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).