Receiver circuit and system using the same

Patent metadata

Field	Value
Publication number	US-9859932-B2
Application number	US-201615145510-A
Country	US
Kind code	B2
Filing date	May 3, 2016
Priority date	Feb 5, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A receiver circuit may be provided. The receiver circuit may include a first duty cycle adjuster configured to correct a duty cycle of a first output signal pair. The receiver circuit may include a second duty cycle adjuster configured to correct a duty cycle of a second output signal pair, based on the first output signal pair, after the first duty cycle adjuster performs a correction on the duty cycle of the first output signal pair.

First claim

What is claimed is:

1. A receiver circuit comprising:
a first amplification circuit configured to differentially amplify first and second input signals and generate a first output signal pair;
a first duty cycle adjuster configured to correct a duty cycle of the first output signal pair based on a duty correction code;
at least one amplification circuit configured to differentially amplify the first output signal pair;
a second amplification circuit configured to differentially amplify the output of the at least one amplification circuit and generate a second output signal pair; and
a second duty cycle adjuster configured to correct a duty cycle of the second output signal pair based on the duty correction code,
wherein the second amplification circuit is complementary type differential amplifier with the first amplification circuit.

2. The receiver circuit according to claim 1 , wherein an amplitude of the first and second input signals are less than an amplitude of the first output signal pair.

3. The receiver circuit according to claim 1 , wherein a duty correction rate per unit time by the first duty cycle adjuster is greater than a duty correction rate per unit time by the second duty cycle adjuster.

4. The receiver circuit according to claim 1 , wherein the first duty cycle adjuster has a first duty correction strength, and the second duty cycle adjuster has a second duty correction strength different from the first duty correction strength.

5. The receiver circuit according to claim 1 , wherein the first duty cycle adjuster provides a first duty correction current generated based on the duty correction code, to the first amplification circuit.

6. The receiver circuit according to claim 5 , wherein the second duty cycle adjuster provides a second duty correction current generated based on the duty correction code, to the second amplification circuit.

7. The receiver circuit according to claim 1 , wherein the first amplification circuit is a P-type differential amplifier.

8. The receiver circuit according to claim 7 , wherein the second amplification circuit is an N-type differential amplifier.

9. The receiver circuit according to claim 1 , wherein the second input signal is a differential signal of the first input signal.

10. The receiver circuit according to claim 1 , wherein the second input signal is a reference voltage which has a voltage level corresponding to a middle of a swing width of the first input signal.

11. A receiver circuit comprising:
a first stage buffer configured to differentially amplify first and second input signals;
a second stage buffer configured to amplify an output signal pair of the first stage buffer;
a third stage buffer configured to amplify an output signal pair of the second stage buffer;
a first duty cycle adjuster configured to generate a first duty correction current to the first stage buffer; and
a second duty cycle adjuster configured to generate a second duty correction current to the third stage buffer,
wherein the third stage buffer is complementary type differential amplifier with the first stage buffer.

12. The receiver circuit according to claim 11 , wherein one or more of the first and second stage buffers are P-type differential amplifiers.

13. The receiver circuit according to claim 11 , wherein one or more of the second and third stage buffers are N-type differential amplifiers.

14. The receiver circuit of claim 11 , further comprising:
a slicer configured to buffer an output signal pair of the third stage buffer and generate a final output signal pair.

15. The receiver circuit according to claim 11 , wherein the second input signal is a differential signal of the first input signal.

16. The receiver circuit according to claim 11 , wherein the second input signal is a reference voltage which has a voltage level corresponding to a middle of a swing width of the first input signal.

17. The receiver circuit according to claim 11 , wherein a duty correction rate per unit time by the first duty cycle adjuster is greater than a duty correction rate per unit time by the second duty cycle adjuster.

18. The receiver circuit according to claim 11 , wherein the first duty cycle adjuster has a first duty correction strength, and the second duty cycle adjuster has a second duty correction strength different from the first duty correction strength.

19. The receiver circuit according to claim 11 , wherein the first and second duty cycle adjusters are configured to generate the first and second duty correction currents, respectively, based on a duty correction code.

Assignees

• Sk Hynix Inc

Inventors

• Hwang Kyu Dong

Classifications

• H03F2200/351

  Pulse width modulation being used in an amplifying circuit · CPC title

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F1/3211

  in differential amplifiers · CPC title

• H03F2203/45652

  the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade · CPC title