Amplification circuit adjusting duty cycle of output signal

Patent metadata

Field	Value
Publication number	US-9362867-B2
Application number	US-201414458386-A
Country	US
Kind code	B2
Filing date	Aug 13, 2014
Priority date	May 8, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

An amplification circuit includes an input portion, a first load portion, a second load portion, and a duty cycle adjustment portion. The input portion changes a voltage level of an output node, which outputs a voltage level thereof as an output signal, in response to an input signal. The first load portion and a second load portion are coupled to the output node. The duty cycle adjustment portion is coupled between the first load portion and the second load portion, and provides a correction current to the output node.

First claim

What is claimed is:

1. An amplification circuit comprising:
an output node configured to output a voltage level thereof as an output signal;
an input portion configured to change the voltage level of the output node in response to an input signal;
a first load portion and a second load portion coupled to the output node; and
a duty cycle adjustment portion coupled between the first load portion and the second load portion and configured to provide a correction current to the output node through the first load portion.

2. The amplification circuit of claim 1 , wherein a resistance value of the first load portion is greater than a resistance value of the second load value.

3. The amplification circuit of claim 1 , wherein the duty cycle adjustment portion comprises:
a duty cycle control unit configured to generate a current offset control signal; and
a current control unit configured to generate the correction current in response to the current offset control signal.

4. The amplification circuit of claim 3 , wherein the duty cycle control unit receives the output signal, detects duty cycle of the output signal, and generates the current offset control signal.

5. The amplification circuit of claim 3 , wherein the current control unit comprises a plurality of drivers configured to provide various amount of current in response to the current offset control signal.

6. The amplification circuit of claim 1 , wherein the second load portion has a resistance value varying in response to a variable resistance code.

7. An amplification circuit comprising:
an output node configured to output a voltage level thereof as an output signal;
an input portion coupled to a first voltage supply node, and configured to change the voltage level of the output node in response to an input signal;
first and second load portions coupled to each other, wherein the first load portion is coupled to the output node and the second load portion is coupled to a second voltage supply node; and
a duty cycle adjustment portion coupled to the output node through the first load portion, and configured to provide a correction current to the output node through the first load portion.

8. The amplification circuit of claim 7 ,
wherein the first load portion is coupled to the output node at a first node thereof, and to a first node of the second load portion at a second node thereof, and
wherein the second load portion is coupled to the second voltage node at a second node thereof.

9. The amplification circuit of claim 8 , wherein a resistance value of the first load portion is greater than a resistance value of the second load value.

10. The amplification circuit of claim 8 , wherein the duty cycle adjustment portion is coupled to a node which connects the first load portion and the second load portion.

11. The amplification circuit of claim 7 , wherein the duty cycle adjustment portion comprises:
a duty cycle control unit configured to generate a current offset control signal; and
a current control unit configured to generate the correction current in response to the current offset control signal.

12. The amplification circuit of claim 11 , wherein the duty cycle control unit receives the output signal, detects duty cycle of the output signal, and generates the current offset control signal.

13. The amplification circuit of claim 11 , wherein the current control unit comprises a plurality of drivers configured to provide various amount of current in response to the current offset control signal.

14. The amplification circuit of claim 7 , wherein the second load portion has a resistance value varying in response to a variable resistance code.

15. An amplification circuit comprising:
an output node configured to output a voltage level thereof as an output signal;
a duty cycle adjustment portion configured to provide a duty correction current to the output node; and
a first load portion configured to electrically connect the output node and the duty cycle adjustment portion and provide an indirect electrical-connection between the output node and the duty cycle adjustment portion,
wherein the duty cycle adjustment portion provides the duty correction current to the output node through the first load portion.

16. The amplification circuit of claim 15 , wherein the output node comprises a first output node, which is configured to output an output signal, and a second output node, which is configured to output a complementary signal of the output signal.

17. The amplification circuit of claim 16 , wherein the first load portion comprises a first resistor, which is connected to the first output node, and a second resistor, which is connected to the second output node.

18. The amplification circuit of claim 16 , wherein the first load portion comprises a first transistor, a drain of which is connected to the first output node, a second transistor, a drain of which is connected to the second output node, a first resistor, which connects the first output node to gates of the first and second transistors, and a second resistor, which connects the second output node to the gates of the first and second transistors.

19. The amplification circuit of claim 15 , wherein the duty cycle adjustment portion comprises:
a duty cycle control unit configured to generate a current offset control signal; and
a current control unit configured to generate the correction current in response to the current offset control signal.

20. The amplification circuit of claim 15 , wherein the duty cycle control unit receives the output signal, detects duty cycle of the output signal, and generates the current offset control signal, and wherein the current control unit comprises a plurality of drivers configured to provide various amount of current in response to the current offset control signal.

Assignees

• Sk Hynix Inc

Inventors

• Yang Jae Mo

Classifications

• H03F3/16

  with field-effect devices · CPC title

• H03F1/30 Primary

  Modifications of amplifiers to reduce influence of variations of temperature or supply voltage {or other physical parameters (in differential amplifiers H03F3/45479)} · CPC title

• H03F3/185

  with field-effect devices (H03F3/187 takes precedence) · CPC title

• H03F2200/375

  Circuitry to compensate the offset being present in an amplifier · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title