Field-effect transistor, and memory and semiconductor circuit including the same

Patent metadata

Field	Value
Publication number	US-9859443-B2
Application number	US-201615362903-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Mar 25, 2011
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.

First claim

What is claimed is:

1. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to a channel length direction of the transistor;
a source electrode in contact with the oxide semiconductor;
a drain electrode in contact with the oxide semiconductor; and
a gate electrode with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the gate electrode partly overlaps the source electrode, and
wherein the gate electrode partly overlaps the drain electrode.

2. The semiconductor device according to claim 1 , wherein part of the oxide semiconductor comprises an N-type region comprising nitrogen, boron, or phosphorus.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Sn-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, and an In—Sn—Ga—Zn-based oxide.

4. The semiconductor device according to claim 1 , wherein a corner portion of the oxide semiconductor has a curved shape.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor has crystallinity.

6. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor comprises a region including crystals, and
wherein c-axes of the crystals in the region are substantially perpendicular to a surface of the oxide semiconductor.

7. A random access memory comprising the transistor according to claim 1 as a cell transistor.

8. A memory comprising the transistor according to claim 1 as a writing transistor.

9. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to a channel length direction of the transistor;
a source electrode electrically connected to the oxide semiconductor;
a drain electrode electrically connected to the oxide semiconductor; and
a gate electrode with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the gate electrode partly overlaps the source electrode, and
wherein the gate electrode partly overlaps the drain electrode.

10. The semiconductor device according to claim 9 , wherein part of the oxide semiconductor comprises an N-type region comprising nitrogen, boron, or phosphorus.

11. The semiconductor device according to claim 9 , wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Sn-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, and an In—Sn—Ga—Zn-based oxide.

12. The semiconductor device according to claim 9 , wherein a corner portion of the oxide semiconductor has a curved shape.

13. The semiconductor device according to claim 9 , wherein the oxide semiconductor has crystallinity.

14. The semiconductor device according to claim 9 ,
wherein the oxide semiconductor comprises a region including crystals, and
wherein c-axes of the crystals in the region are substantially perpendicular to a surface of the oxide semiconductor.

15. A random access memory comprising the transistor according to claim 9 as a cell transistor.

16. A memory comprising the transistor according to claim 9 as a writing transistor.

17. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to a channel length direction of the transistor;
a source electrode electrically connected to the oxide semiconductor;
a drain electrode electrically connected to the oxide semiconductor; and
a gate electrode with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the source electrode partly overlaps the oxide semiconductor, and
wherein the drain electrode partly overlaps the oxide semiconductor.

18. The semiconductor device according to claim 17 , wherein part of the oxide semiconductor comprises an N-type region comprising nitrogen, boron, or phosphorus.

19. The semiconductor device according to claim 17 , wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Sn-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, and an In—Sn—Ga—Zn-based oxide.

20. The semiconductor device according to claim 17 , wherein a corner portion of the oxide semiconductor has a curved shape.

21. The semiconductor device according to claim 17 , wherein the oxide semiconductor has crystallinity.

22. The semiconductor device according to claim 17 ,
wherein the oxide semiconductor comprises a region including crystals, and
wherein c-axes of the crystals in the region are substantially perpendicular to a surface of the oxide semiconductor.

23. A random access memory comprising the transistor according to claim 17 as a cell transistor.

24. A memory comprising the transistor according to claim 17 as a writing transistor.

25. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to a channel length direction of the transistor;
a source electrode electrically connected to the oxide semiconductor;
a drain electrode electrically connected to the oxide semiconductor; and
a gate electrode with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the oxide semiconductor includes a first N-type region and a second N-type region, and
wherein the first N-type region and the second N-type region are formed in a self-aligned manner with respect to the gate electrode.

26. The semiconductor device according to claim 25 , wherein the first N-type region and the second N-type region contains nitrogen, boron, or phosphorus.

27. The semiconductor device according to claim 25 , wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an A

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Godo Hiromichi
• Takemura Yasuhiko

Classifications

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic

• H01L29/78609

  Electricity · mapped topic

• H01L27/108

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic