Field-effect transistor including oxide semiconductor, and memory and semiconductor circuit including the same

Patent metadata

Field	Value
Publication number	US-9548395-B2
Application number	US-201514848515-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Mar 25, 2011
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.

First claim

What is claimed is:

1. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, a top surface and side surfaces, the side surfaces extending in a channel length direction of the transistor, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to the channel length direction;
a source electrode in contact with at least the top surface of the oxide semiconductor;
a drain electrode in contact with at least the top surface of the oxide semiconductor; and
a gate electrode along the top surface and the side surfaces with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the gate electrode partly overlaps the source electrode, and
wherein the gate electrode partly overlaps the drain electrode.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Sn-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, and an In—Sn—Ga—Zn-based oxide.

3. A random access memory comprising the transistor according to claim 1 as a cell transistor.

4. A memory comprising the transistor according to claim 1 as a writing transistor.

5. The semiconductor device according to claim 1 , wherein a corner portion of the oxide semiconductor has a curved shape.

6. The semiconductor device according to claim 1 , wherein the oxide semiconductor has crystallinity.

7. The semiconductor device according to claim 1 , wherein part of the oxide semiconductor comprises an N-type region comprising nitrogen, boron, or phosphorus.

8. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor comprises a first region including crystals, and
wherein c-axes of the crystals in the first region are substantially perpendicular to a surface of the oxide semiconductor.

9. The semiconductor device according to claim 8 ,
wherein the first region is in contact with the top surface of the oxide semiconductor,
wherein the oxide semiconductor comprises a second region being in contact with one of the side surfaces of the oxide semiconductor,
wherein the second region includes crystals, and
wherein c-axes of the crystals in the second region are substantially perpendicular to the one of the side surfaces of the oxide semiconductor.

10. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, a top surface and side surfaces, the side surfaces extending in a channel length direction of the transistor, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to the channel length direction;
a source electrode in contact with at least the top surface of the oxide semiconductor;
a drain electrode in contact with at least the top surface of the oxide semiconductor; and
a gate electrode along the top surface and the side surfaces with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the source electrode is in contact with the side surfaces of the oxide semiconductor,
wherein the drain electrode is in contact with the side surfaces of the oxide semiconductor,
wherein the gate electrode partly overlaps the source electrode, and
wherein the gate electrode partly overlaps the drain electrode.

11. The semiconductor device according to claim 10 , wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Sn-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, and an In—Sn—Ga—Zn-based oxide.

12. A random access memory comprising the transistor according to claim 10 as a cell transistor.

13. A memory comprising the transistor according to claim 10 as a writing transistor.

14. The semiconductor device according to claim 10 , wherein a corner portion of the oxide semiconductor has a curved shape.

15. The semiconductor device according to claim 10 , wherein the oxide semiconductor has crystallinity.

16. The semiconductor device according to claim 10 , wherein part of the oxide semiconductor comprises an N-type region comprising nitrogen, boron, or phosphorus.

17. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor comprises a first region including crystals, and
wherein c-axes of the crystals in the first region are substantially perpendicular to a surface of the oxide semiconductor.

18. The semiconductor device according to claim 17 ,
wherein the first region is in contact with the top surface of the oxide semiconductor,
wherein the oxide semiconductor comprises a second region being in contact with one of the side surfaces of the oxide semiconductor,
wherein the second region includes crystals, and
wherein c-axes of the crystals in the second region are substantially perpendicular to the one of the side surfaces of the oxide semiconductor.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Godo Hiromichi
• Takemura Yasuhiko

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6706

  for preventing leakage current  (TFTs characterised by the properties of the source or drain H10D30/6713) · CPC title