Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

Patent metadata

Field	Value
Publication number	US-9859381-B2
Application number	US-201514844332-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	May 17, 2005
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate comprising a first crystalline semiconductor material having a top surface with a first crystal orientation, the substrate including a recess from the top surface into the substrate with a maximum depth d, wherein all of the recessed surfaces of the recess have a second crystal orientation different from the first crystal orientation;
a dielectric sidewall of height h disposed on the top surface of the substrate and proximate the recess; and
a second crystalline semiconductor material of a maximum width w disposed in the recess, the recess defining an interface between the second crystalline semiconductor material and the substrate, wherein the second crystalline material physically contacts all of the recessed surfaces of the recess,
wherein the second crystalline semiconductor material has a lattice mismatch with the first crystalline semiconductor material, the lattice mismatch causes defects in the second crystalline semiconductor material, and the defects terminate at a distance H above a bottom surface of the recess.

2. The semiconductor structure of claim 1 , wherein H is less than h+d.

3. The semiconductor structure of claim 2 , wherein H is less than d.

4. The semiconductor structure of claim 1 , wherein H is less than or equal to w.

5. The semiconductor structure of claim 1 , wherein a ratio of h+d to w is greater than or equal to one.

6. The semiconductor structure of claim 1 , wherein the recess has a v-shaped profile.

7. The semiconductor structure of claim 1 , wherein the first crystal orientation is (100), and the second crystal orientation is not (100).

8. The semiconductor structure of claim 7 , wherein the second crystal orientation is (111).

9. The semiconductor structure of claim 1 , further comprising a third crystalline semiconductor material disposed above the second crystalline semiconductor material.

10. The semiconductor structure of claim 9 , wherein the third crystalline semiconductor material is lattice mismatched to the second crystalline semiconductor material, and the lattice mismatch between the second crystalline semiconductor material and the first crystalline semiconductor material is less than a lattice mismatch between the third crystalline semiconductor material and the first crystalline semiconductor material.

11. The semiconductor structure of claim 9 , wherein a boundary defined by the interface between the second crystalline semiconductor material and the third crystalline semiconductor material is proximate a boundary defined by an interface between the substrate and the dielectric sidewall.

12. The semiconductor structure of claim 1 , further comprising a photonic structure disposed at least partially above the second crystalline semiconductor material.

13. The semiconductor structure of claim 1 , further comprising a photonic structure disposed at least partially inside the recess.

14. The semiconductor structure of claim 1 , further comprising a third crystalline semiconductor material disposed over the second crystalline semiconductor material, wherein a bandgap of the third crystalline semiconductor material is lower than a bandgap of the second crystalline semiconductor material.

15. The semiconductor structure of claim 1 , further comprising a third crystalline semiconductor material disposed over the second crystalline semiconductor material, wherein the second crystalline semiconductor material is n-doped and the third crystalline semiconductor material is p-doped.

16. The semiconductor structure of claim 1 , further comprising a third crystalline semiconductor material disposed over the second crystalline semiconductor material, wherein the second crystalline semiconductor material is GaAs and the third crystalline semiconductor material is lnP.

17. A semiconductor structure comprising:
a first substrate comprising a first crystalline semiconductor material having a top surface and a bottom surface opposite from the top surface, the first substrate including a recess extending from the top surface into the first substrate, wherein a side surface of the recess has a different crystal orientation than the top surface of the first substrate;
a dielectric layer on the top surface of the first substrate, an opening extending through the dielectric layer to the recess, wherein a height of the dielectric layer above the top surface of the first substrate is greater than the depth the recess extends from the top surface into the first substrate; and
a second crystalline semiconductor material in the recess and the opening, the second crystalline semiconductor material being lattice mismatched to the first crystalline semiconductor material, the lattice mismatch causing defects in the second crystalline semiconductor material, the defects terminating in at least one of the recess or the opening;
a photonic device on the second crystalline semiconductor material;
a second substrate bonded to the photonic device;
a first metal contact layer on the second substrate; and
a second metal contact layer on the bottom surface of the first substrate.

18. The semiconductor structure of claim 17 , wherein the recess of the first substrate has a maximum depth d, the dielectric layer has a height h, the second crystalline semiconductor material has a maximum width w disposed in the recess, the defects terminate at a distance H above a bottom surface of the recess.

19. The semiconductor structure of claim 18 , wherein H is less than d.

20. A semiconductor structure comprising:
a substrate comprising a first crystalline semiconductor material having a top surface with a first crystal orientation, the substrate including a v-shaped recess from the top surface into the substrate, the v-shaped recess comprising a recessed surface with a second crystal orientation;
a dielectric sidewall disposed on the top surface of the substrate and proximate the recess, the dielectric sidewall defining an opening over the v-shaped recess, the dielectric sidewall comprising a dielectric material, wherein the v-shaped recess is free of the dielectric material;
a second crystalline semiconductor material disposed in the recess, the recess defining an interface between the second crystalline semiconductor material and the substrate, the second crystalline semiconductor material having a lattice mismatch with the first crystalline semiconductor material, the lattice mismatch causes defects in the second crystalline semiconductor material, and the defects terminate within at least one of the v-shaped recess or the opening; and
a third crystalline semiconductor material disposed above the second crystalline semiconductor material, the third crystalline semiconductor material being lattice mismatched to the second crystalline semiconductor material, and the lattice mismatch between the second crystalline semiconductor material and the first crystalline semiconductor material is less than a lattice mismatch between the third crystalline semiconductor material and the first crystalline semiconductor material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Jizhong
• Lochtefeld Anthony J

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/2926

  Crystal orientations · CPC title