Semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9859356-B2
Application number	US-201615044121-A
Country	US
Kind code	B2
Filing date	Feb 16, 2016
Priority date	May 27, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.

First claim

What is claimed is:

1. A semiconductor integrated circuit, comprising:
an inductor including one conductive loop; and
a plurality of high permeability patterns disposed adjacent to the conductive loop, wherein the high permeability patterns are composed of nickel, fiber, cobalt, an alloy of the above-mentioned materials, or a combination of the above-mentioned materials and the alloy, wherein the high permeability patterns is further disposed in a region surrounding the conductive loop.

2. The semiconductor integrated circuit according to claim 1 , wherein the inductor further includes a dielectric region adjacent to the conductive loop, and the high permeability patterns at least disposed within the dielectric region.

3. The semiconductor integrated circuit according to claim 2 , wherein the dielectric region is enclosed by the conductive loop.

4. The semiconductor integrated circuit according to claim 1 , wherein each of the high permeability patterns is electrically floating with respect to circuit ground.

5. The semiconductor integrated circuit according to claim 1 , wherein the high permeability patterns are pattern ground shielded and electrically connected to circuit ground.

6. The semiconductor integrated circuit according to claim 1 , wherein the high permeability patterns are arranged as an array.

7. The semiconductor integrated circuit according to claim 1 , wherein a size of the high permeability patterns is equal to a spacing between two of the high permeability patterns adjacent to each other.

8. The semiconductor integrated circuit according to claim 1 , wherein a diameter of the inductor is equal to or more than fifty times of a size of the high permeability patterns.

9. The semiconductor integrated circuit according to claim 1 , wherein a diameter of the inductor is equal to or more than hundredfold of a size of the high permeability patterns.

10. The semiconductor integrated circuit according to claim 1 , wherein a size of the high permeability patterns is about 3 micrometers to about 10 micrometers.

11. The semiconductor integrated circuit according to claim 1 , wherein a thickness of the high permeability patterns is about 2 micrometers.

12. The semiconductor integrated circuit according to claim 1 , wherein the high permeability patterns have geometric shapes.

13. The semiconductor integrated circuit according to claim 12 , wherein the high permeability patterns have square shapes or cross shapes.

14. The semiconductor integrated circuit according to claim 1 , wherein the inductor is an integrated passive device.

15. A semiconductor integrated circuit comprising:
an inductor including one conductive loop; and
a plurality of high permeability patterns disposed adjacent to the conductive loop, wherein the high permeability patterns are composed of nickel, fiber, cobalt, an alloy of the above-mentioned materials, or a combination of the above-mentioned materials and the alloy, and wherein the conductive loop is composed of at least one conductive layer disposed on a substrate, and the high permeability patterns are composed of a high permeability layer disposed on the substrate.

16. The semiconductor integrated circuit according to claim 15 , wherein the high permeability layer is disposed in a vertical direction between the conductive layer and the substrate.

17. The semiconductor integrated circuit according to claim 15 , wherein the conductive layer is disposed in a vertical direction between the high permeability layer and the substrate.

18. The semiconductor integrated circuit according to claim 15 , wherein the conductive loop is composed of at least two conductive layers disposed on the substrate, and the high permeability layer is disposed between the two conductive layers in a projection direction perpendicular to a surface of the substrate.

Assignees

• Mediatek Inc
• Mediatek Inc

Inventors

• Tsai Ming-Da
• Lee Tao-Yi
• Hung Cheng-Chou
• Lee Tung-Hsing

Classifications

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H01L23/5227

  Electricity · mapped topic

• H01L28/10 Primary

  Electricity · mapped topic

• H10D1/20 Primary

  Inductors · CPC title