Stack-type semiconductor device

Patent metadata

Field	Value
Publication number	US-9859321-B2
Application number	US-201615333382-A
Country	US
Kind code	B2
Filing date	Oct 25, 2016
Priority date	Oct 29, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A stack-type semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower interconnection on the lower substrate, a lower pad on the lower interconnection, and a lower interlayer insulating layer covering side surfaces of the lower interconnection and the lower pad. The upper device includes an upper substrate, an upper interconnection under the upper substrate, an upper pad under the upper interconnection, and an upper interlayer insulating layer covering side surfaces of the upper interconnection and the upper pad. Each of the pads has a thick portion and a thin portion. The thin portions of the pads are bonded to each other, the thick portion of the lower pad contacts the bottom of the upper interlayer insulating layer, and the thick portion of the upper pad contacts the top of the lower interlayer insulating layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a lower device including a lower substrate, a lower interconnection structure on the lower substrate, a lower pad on the lower interconnection structure, and a lower interlayer insulation covering side surfaces of the lower interconnection structure and of the lower pad; and
an upper device disposed on the lower device and including an upper substrate, an upper interconnection structure under the upper substrate, an upper pad under the upper interconnection structure, and an upper interlayer insulation covering side surfaces of the upper interconnection structure and of the upper pad, and
wherein the lower pad has a first portion and a second portion, the first portion of the lower pad being thicker, in a vertical direction, than the second portion of the lower pad,
the upper pad has a first portion and a second portion, the first portion of the upper pad being thicker, in the vertical direction, than the second portion of the upper pad, and
the second portion of the lower pad is bonded to the upper pad at the second portion of the upper pad, the first portion of the lower pad is in contact with a lower surface of the upper interlayer insulation, and the first portion of the upper pad is in contact with an upper surface of the lower interlayer insulation.

2. The semiconductor device of claim 1 , wherein:
the second portion of the lower pad has a first side vertically overlapping the second portion of the upper pad and a second side vertically overlapping the upper interlayer insulation; and
the second portion of the upper pad includes a first side vertically overlapping the second portion of the lower pad and a second side overlapping the lower interlayer insulation.

3. The semiconductor device of claim 2 , wherein:
the first portion of the lower pad is connected to the second side of the second portion of the lower pad; and
the first portion of the upper pad is connected to the second side of the second portion of the upper pad.

4. The semiconductor device of claim 3 , wherein the first portion of the lower pad and the first portion of the upper pad are disposed along a diagonal direction that is inclined relative to the vertical.

5. The semiconductor device of claim 1 , wherein:
the lower interlayer insulation includes a first lower interlayer insulating layer covering side surfaces of the lower interconnection structure and a second lower interlayer insulating layer covering side surfaces of the lower pad; and
the upper interlayer insulation includes a first upper interlayer insulating layer covering side surfaces of the upper interconnection structure and a second upper interlayer insulating layer covering side surfaces of the upper pad.

6. The semiconductor device of claim 5 , wherein:
the second lower interlayer insulating layer spans an upper surface of the lower interconnection structure and a lower surface of the second portion of the lower pad; and
the second upper interlayer insulating layer spans a lower surface of the upper interconnection structure and an upper surface of the second portion of the upper pad.

7. The semiconductor device of claim 1 , wherein the upper pad is laterally offset in a first direction from the lower pad.

8. The semiconductor device of claim 7 , wherein the first portion of the lower pad and the first portion of the upper pad have forms, as viewed in plan, that are elongated in a second direction perpendicular to the first direction.

9. The semiconductor device of claim 1 , wherein the upper pad is laterally offset in a first direction and a second direction perpendicular to the first direction with respect to the lower pad.

10. The semiconductor device of claim 9 , wherein each of the first portion of the lower pad and the first portion of the upper pad have sections that intersect at a right angle and are elongated in the first direction and the second direction, respectively.

11. The semiconductor device of claim 1 , further comprising:
a photodiode inside the upper substrate;
a passivation layer disposed on the upper substrate;
a color filter disposed on the passivation layer and vertically aligned with the photodiode; and
a micro-lens disposed on the color filter.

12. The semiconductor device of claim 11 , further comprising:
a transmission gate electrode adjacent to the photodiode on the upper substrate; and
a lower gate electrode disposed on the lower substrate.

13. A semiconductor device comprising:
a lower substrate;
a lower interconnection structure disposed on the lower substrate;
a lower pad disposed on the lower interconnection structure, wherein the lower pad has a first portion that is in contact with the lower interconnection structure, and a second portion that is connected to an upper portion of one side of the first portion of the lower pad, the second portion of the lower pad being thinner than the first portion of the lower pad in a vertical direction;
an upper pad disposed on the lower pad, wherein the upper pad has a first portion, and a second portion that is connected to a lower portion of one side of the first portion of the upper pad and is bonded to the second portion of the lower pad, the second portion of the upper pad being thinner than the first portion of the upper pad in the vertical direction;
an upper interconnection structure disposed on the upper pad and in contact with the first portion of the upper pad; and
an upper substrate disposed on the upper interconnection structure,
wherein the first portion of the lower pad and the first portion of the upper pad are disposed along a diagonal direction that is inclined relative to the vertical direction.

14. The semiconductor device of claim 13 , further comprising:
a first lower interlayer insulating layer disposed on the lower substrate and covering side surfaces of the lower interconnection;
a second lower interlayer insulating layer disposed on the first lower interlayer insulating layer and covering lower side surfaces of the first portion of the lower pad;
a lower junction insulating layer disposed on the second lower interlayer insulating layer and covering upper side surfaces of the first portion of the lower pad and side surfaces of the second portion of the lower pad;
a first upper interlayer insulating layer disposed under the upper substrate and covering side surfaces of the upper interconnection;
a second upper interlayer insulating layer disposed under the first upper interlayer insulating layer and covering upper side surfaces of the first portion of the upper pad; and
an upper junction insulating layer disposed under the second upper interlayer insulating layer and covering side surfaces of the first portion of the upper pad and side surfaces of the second portion of the upper pad.

15. The semiconductor device of claim 14 , wherein:
the lower junction insulating layer has a molecular structure denser than molecular structures of the first lower interlayer insulating layer and the second lower interlayer insulating layer; and
the upper junction insulating layer has a molecular structure denser than molecular structures of the first upper interlayer insulating layer and the second upper interlayer insulating layer.

16. A semiconductor device comprising:
a lower semiconductor substrate;
a lower interlayer insulation disposed on the lower semiconductor substrate and having an upper surface;
an upper interlayer insulation disposed on the lower interlayer insulation and having a lower surface constituting an interface with the upper surface of the lower interla

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Donghyun
• Kwon Doowon

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/347

  Dispositions of multiple die-attach connectors · CPC title

• H10W72/344

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H01L27/1464

  Electricity · mapped topic