Bridging local semiconductor interconnects

Patent metadata

Field	Value
Publication number	US-9859303-B2
Application number	US-201615274403-A
Country	US
Kind code	B2
Filing date	Sep 23, 2016
Priority date	Nov 11, 2013
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a plurality of transistor gates comprising one or more inner gates and a plurality of outer gates, the plurality of transistor gates at least directly upon a buried-dielectric layer of a semiconductor substrate, the semiconductor substrate comprising a plurality of outer active areas and one or more inner active areas, wherein the plurality of outer active areas are of opposite polarity relative to the one or more inner active areas;
an isolator directly upon the one or more inner gates associated with the one or more inner active areas and offset from the plurality of outer active areas, the isolator comprising a protective barrier portion directly upon a dielectric layer, the dielectric layer directly upon the one or more inner gates; and
a monolithic contact bar electrically connecting the plurality of outer active areas, the monolithic contact bar directly upon the protective barrier portion, wherein the isolator electrically insulates the monolithic contact bar from the one or more inner gates.

2. The semiconductor device of claim 1 , wherein the isolator also insulates the monolithic contact bar from the one or more inner active areas.

3. The semiconductor device of claim 1 , further comprising an interlayer dielectric, wherein a top surface of the monolithic contact bar and a top surface of the interlayer dielectric are coplanar.

4. The semiconductor device of claim 1 , wherein the semiconductor substrate is a silicon on insulator (SOI) substrate.

5. The semiconductor device of claim 1 , wherein the semiconductor substrate is a bulk substrate.

6. A semiconductor device comprising:
a plurality of transistor gates comprising one or more inner gates and a plurality of outer gates, the plurality of transistor gates at least directly upon a buried-dielectric layer of a semiconductor substrate;
an isolator directly upon the one or more inner gates and offset from the plurality of outer active areas, the isolator comprising a protective barrier portion directly upon a dielectric layer, the dielectric layer at least directly upon the one or more inner gates; and
a monolithic contact bar electrically connecting the plurality of outer gates, the monolithic contact bar directly upon the protective barrier portion, wherein the isolator electrically insulates the monolithic contact bar from the one or more inner gates.

7. The semiconductor device of claim 6 , further comprising an interlayer dielectric, wherein a top surface of the monolithic contact bar and a top surface of the interlayer dielectric are coplanar.

8. The semiconductor device of claim 6 , wherein the semiconductor substrate is a silicon on insulator (SOI) substrate.

9. The semiconductor device of claim 6 , wherein the semiconductor substrate is a bulk substrate.

10. A semiconductor device fabrication method comprising:
forming a plurality of transistor gates comprising one or more inner gates and a plurality of outer gates at least directly upon a buried-dielectric layer of a semiconductor substrate, the semiconductor substrate comprising a plurality of outer active areas and one or more inner active areas, wherein the plurality of outer active areas are of opposite polarity relative to the one or more inner active areas;
forming an isolator directly upon the one or more inner gates offset from the plurality of outer active areas, the isolator comprising a protective barrier portion formed directly upon a dielectric layer formed at least directly upon the one or more inner gates; and
forming a monolithic contact bar electrically connecting the plurality of outer active areas directly upon the protective barrier portion, wherein the isolator electrically insulates the monolithic contact bar from the one or more inner gates.

11. The semiconductor device fabrication method of claim 10 , wherein the isolator also insulates the monolithic contact bar from the one or more inner active areas.

12. The semiconductor device fabrication method of claim 10 , further comprising:
forming an interlayer dielectric, wherein a top surface of the monolithic contact bar and a top surface of the interlayer dielectric are coplanar.

13. The semiconductor device fabrication method of claim 10 , wherein the semiconductor substrate is a silicon on insulator (SOI) substrate.

14. The semiconductor device fabrication method of claim 10 , wherein the semiconductor substrate is a bulk substrate.

15. The semiconductor device fabrication method of claim 10 , wherein the plurality of outer active areas and the one or more inner active areas are source/drain regions.

Assignees

• IBM
• St Microelectronics Inc

Inventors

• Li Wai-Kin
• Lin Chieh-Yu
• Daurelle Yannick

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/084

  for dual-damascene structures · CPC title