Registration mark formation during sidewall image transfer process

Patent metadata

Field	Value
Publication number	US-9859224-B2
Application number	US-201615239166-A
Country	US
Kind code	B2
Filing date	Aug 17, 2016
Priority date	Feb 25, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

First claim

What is claimed is:

1. A method of forming a registration mark during formation of sub-lithographic structures on a substrate, the method comprising the steps of:
forming a plurality of mandrels over a hard mask over a semiconductor layer;
forming a conformal spacer material covering a top and side of the mandrels and in between the mandrels;
selecting at least one selected mandrel and forming a mask over the at least one selected mandrel;
forming a spacer adjacent each of an uncovered group of the plurality of the mandrels that are uncovered by the mask;
removing the uncovered group of mandrels uncovered by the mask leaving the spacers, while preventing removal of the at least one selected mandrel using the mask;
removing the mask;
first etching to pattern the sub-lithographic structures into the hard mask, using the spacers as a pattern of the sub-lithographic structure; and
second etching to: form the sub-lithographic structures in the semiconductor layer using the patterned hard mask, and form the registration mark over the semiconductor layer using the at least one selected mandrel.

2. The method of claim 1 , wherein the second etching includes etching to remove the spacers and etching the semiconductor layer using the patterned hard mask and the at least one selected mandrel as a mask.

3. The method of claim 1 , wherein each mandrel includes a material selected from the group consisting of: polysilicon, amorphous silicon or amorphous carbon.

4. The method of claim 1 , further comprising forming a lithographic semiconductor structure using the mask in a region of the substrate distal to the sub-lithographic structures.

5. The method of claim 1 , wherein the forming of the plurality of mandrels over a semiconductor layer and the spacer forming includes:
depositing and patterning a material into the plurality of mandrels;
depositing a spacer layer over each mandrel; and
etching to form the spacer adjacent each of the plurality of mandrels, expose a surface of the hard mask between the mandrels and expose a top of each mandrel.

6. The method of claim 1 , wherein the forming of the plurality of mandrels, the mask forming and the spacer forming includes:
depositing and patterning a material into the plurality of mandrels;
depositing a spacer layer over each mandrel;
selecting the at least one selected mandrel and forming the mask over the at least one selected mandrel of the plurality of mandrels; and
etching to form the spacers adjacent each of the uncovered group of the plurality of mandrels uncovered by the mask, expose a surface of the hard mask between the uncovered group of the plurality of mandrels and expose a top of each of the uncovered group of the plurality of mandrels.

7. The method of claim 6 , wherein a portion of the spacer layer over the hard mask and adjacent each mandrel is covered by the mask.

8. The method of claim 6 , wherein the registration mark includes a portion of each mandrel covered by the mask.

9. The method of claim 1 , wherein the hard mask includes a silicon nitride layer and a silicon oxide layer.

10. The semiconductor structure of claim 9 , further comprising a lithographic semiconductor structure in a region of the substrate distal to the sub-lithographic structures.

11. The semiconductor structure of claim 9 , wherein the registration mark includes:
a mandrel over a hard mask over a semiconductor layer, the semiconductor layer being wider than the mandrel and the hard mask.

12. A semiconductor structure on a substrate, the semiconductor structure comprising:
a registration mark including lithographic sized features; and
a plurality of sub-lithographic structures adjacent to the registration mark,
wherein the registration mark includes sections of a semiconductor layer, each section having a width greater than a width of each of the plurality of sub-lithographic structures.

Assignees

• IBM

Inventors

• Conklin David J
• Gabor Allen H
• Kanakasabapathy Sivananda K
• Kim Byeong Y
• Lie Fee Li
• Sieg Stuart A

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/283

  by chemical means · CPC title