Zero transistor transverse current bi-directional bitcell

Patent metadata

Field	Value
Publication number	US-9858975-B1
Application number	US-201615385828-A
Country	US
Kind code	B1
Filing date	Dec 20, 2016
Priority date	Aug 24, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A bitcell for storing a charge state, the bitcell including a spin hall metal for passing through a charge current, a magneto tunnel junction (MTJ) stack for generating and storing a non-volatile spin state corresponding to a binary bit in response to passage of the charge current through the spin hall metal, and for inducing the charge current corresponding to the non-volatile spin state in response to application of a read voltage, first and second write bitlines for sourcing the charge current through the spin hall metal in response to a write voltage being applied to both of the first and second write bitlines, and a read bitline for inducing the charge current through the spin hall metal in response to the read voltage being applied to the read bitline, and a first wordline and a second wordline for permitting a flow of the charge current through spin hall metal.

First claim

What is claimed is:

1. A transverse current bi-directional bitcell coupled to an external circuit and configured to store a charge state, the transverse current bi-directional bitcell comprising:
a spin hall metal configured to pass through a charge current;
a magneto tunnel junction (MTJ) stack on the spin hall metal and configured to generate and store a non-volatile spin state corresponding to a binary bit in response to passage of the charge current through the spin hall metal, and to generate the charge current corresponding to the non-volatile spin state in response to application of a read voltage;
a first write bitline and a second write bitline electrically isolated from the first write bitline, the first and second write bitlines being electrically coupled to the spin hall metal via a pair of write diodes having opposite polarity, the first and second write bitlines being configured to source the charge current through the spin hall metal, during a write operation, in response to a write voltage being applied to both of the first and second write bitlines; and
a read bitline electrically coupled to the MTJ stack via a read diode, the read bitline being configured to induce the charge current through the spin hall metal, during a read operation, in response to the read voltage being applied to the read bitline; and
a first wordline and a second wordline electrically coupled to the spin hall metal via a pair of access diodes having opposite polarity and configured to permit a flow of the charge current through spin hall metal in response to a wordline voltage being applied to both the first and second wordlines.

2. A transverse current bi-directional bitcell of claim 1 , wherein the first write bitline is electrically isolated from the second write bitline, and
wherein the second wordline is electrically isolated from the first wordline.

3. A transverse current bi-directional bitcell of claim 1 , wherein the spin hall metal exhibits a large spin hall angle such that a density of spin torque current flowing through the MTJ stack is larger than that of the transverse charge current flowing through the spin hall metal.

4. A transverse current bi-directional bitcell of claim 1 , wherein the spin hall metal comprises beta tantalum, platinum, and/or copper bismuth.

5. A transverse current bi-directional bitcell of claim 1 , wherein the MTJ stack contacts the spin hall metal at an interface plane, and
wherein the MTJ stack comprises:
a free layer comprising magnetic material and configured to exhibit an easy axis of magnetization parallel with the interface plane, and to respond to a spin current corresponding to the charge current flowing through the spin hall metal based on a giant spin hall effect;
a pinned layer comprising magnetic material and exhibiting a fixed axis of magnetization parallel with the interface plane and unaffected by stray fields resulting from the charge current flowing through the spin hall metal; and
a non-magnetic layer between the free and pinned layers and configured to magnetically isolate a free magnetic moment of the free layer from a fixed magnetic moment of the pinned layer and to maintain any existing difference in directionality of the free and fixed magnetic moments.

6. A transverse current bi-directional bitcell of claim 5 , wherein the MTJ stack has an elliptical cross section along a transverse direction parallel with the interface plane, the elliptical cross section having a long axis in a same direction as a fixed axis of magnetization of the pinned layer.

7. A transverse current bi-directional bitcell of claim 1 , wherein, in response to the charge current flowing through the spin hall metal, the MTJ stack is configured to exhibit magnetic moments having a parallel configuration or anti-parallel configuration, and
wherein the MTJ stacks is configured to maintain the parallel or anti-parallel configuration even when no power is provided to the transverse current bi-directional bitcell.

8. A transverse current bi-directional bitcell of claim 1 , wherein a magnitude of the write voltage is greater than or equal to a forward-bias voltage of the pair of write diodes,
wherein a magnitude of the read voltage is greater than or equal to a forward-bias voltage of the read diodes, and
wherein the wordline voltage being applied to the first and second wordlines is zero volts during the write operation, and has a magnitude greater than or equal to a forward-bias voltage of the pair of access diodes.

9. A transverse current bi-directional bitcell of claim 1 , wherein the first and second write bitlines are coupled to the spin hall metal on one side of the MTJ stack, and the first and second wordlines are coupled to the spin hall metal on an opposite side of the MTJ stack, and
wherein the read bitline is electrically coupled to a pinned layer of the MTJ stack.

10. A transverse current bi-directional bitcell of claim 1 , wherein the first write bitline and the first wordline are coupled to the spin hall metal on one side of the MTJ stack, and the second write bitline and the second wordline are coupled to the spin hall metal on an opposite side of the MTJ stack, and
wherein the read bitline is electrically coupled to a pinned layer of the MTJ stack.

11. A transverse current bi-directional bitcell of claim 1 , wherein the charge current is transverse to a stacking direction of the MTJ stack and does not flow through the MTJ stack during the write operation.

12. A method of controlling an operational state of a transverse current bi-directional bitcell configured to store a charge state using an external circuit and, the method comprising:
selectively applying a write voltage to a first write bitline and a second write bitline that are electrically isolated from each other, the first and second write bitlines being electrically coupled to a spin hall metal via a pair of write diodes having opposite polarity;
selectively applying a read voltage to a read bitline electrically coupled to a magneto tunnel junction (MTJ) stack on the spin hall metal via a read diode; and
selectively applying a first voltage to a first wordline and a second voltage to a second wordline, the first wordline and a second wordline being electrically isolated from each other and being electrically coupled to the spin hall metal via a pair of access diodes having opposite polarity.

13. The method of claim 12 , wherein the MTJ stack contacts the spin hall metal at an interface plane, and
wherein the MTJ stack comprises:
a free layer comprising magnetic material and configured to exhibit an easy axis of magnetization parallel with the interface plane, and to respond to a spin current corresponding to a charge current flowing through the spin hall metal based on a giant spin hall effect;
a pinned layer comprising magnetic material and exhibiting a fixed axis of magnetization parallel with the interface plane and unaffected by stray fields resulting from the charge current flowing through the spin hall metal; and
a non-magnetic layer between the free and pinned layers and configured to magnetically isolate a free magnetic moment of the free layer from a fixed magnetic moment of the pinned layer and to maintain any existing difference in directionality of the free and fixed magnetic moments.

14. The method of claim 12 , further comprising disabling the bitcell by:
reverse-biasing the read diode by applying a negative voltage to the read bitline;
reverse-biasing the pair of write diodes by applying the negative voltage to the first write bitline and applying a positive voltage to the second write bitline; and
reverse

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hatcher Ryan Michael

Classifications

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title