Dynamic design partitioning for diagnosis

Patent metadata

Field	Value
Publication number	US-9857421-B2
Application number	US-201615146761-A
Country	US
Kind code	B2
Filing date	May 4, 2016
Priority date	Nov 18, 2011
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.

First claim

What is claimed is:

1. One or more processor-readable storage device storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
with the one or more processors,
receiving failure information for one or more integrated circuit devices, the failure information resulting from test patterns being applied to the one or more integrated circuit devices;
extracting a sub-circuit from a circuit design for the one or more integrated circuit devices based on the failure information, the sub-circuit comprising one or more portions of the circuit design that include one or more defects in the one or more integrated circuit devices, wherein the extracting comprises combining fan-in cones of failing observation points and adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points, wherein the one or more passing observation points are selected based on one or more relationships with the failing observation points, wherein the one or more relationships are represented by shared gate ratios;
performing fault diagnosis on the sub-circuit to generate diagnosis data based on the test patterns and the failure information; and
outputting the diagnosis data.

2. The one or more processor-readable storage device of claim 1 , wherein the adding is performed if a size of the sub-circuit is smaller than a predetermined value.

3. The one or more processor-readable storage device of claim 1 , wherein the extracting is further based on clock information of the test patterns.

4. The one or more processor-readable storage device of claim 1 , wherein the extracting is further based on layout information of the circuit design.

5. The one or more processor-readable storage device of claim 1 , wherein the extracting and the performing employ different processors for at least one of the one or more integrated circuit devices.

6. A method of fault diagnosis, comprising:
by one or more computers,
receiving information of a circuit design for one or more integrated circuit devices and failure information of the one or more integrated circuit devices generated by applying test patterns to the one or more integrated circuit devices;
extracting a sub-circuit from the circuit design based on the failure information, the sub-circuit comprising one or more portions of the circuit design that include one or more defects in the one or more integrated circuit devices, wherein the extracting comprises combining fan-in cones of failing observation points and adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points, wherein the one or more passing observation points are selected based on one or more relationships with the failing observation points, wherein the at least one of the one or more relationships is represented by one or more shared gate ratios;
performing fault diagnosis on the sub-circuit to generate diagnosis data based on the test patterns and the failure information; and
outputting the diagnosis data.

7. The method of claim 6 , wherein the adding is performed if a size of the sub-circuit is smaller than a predetermined value.

8. The method of claim 6 , wherein the extracting is further based on clock information of the test patterns.

9. The method of claim 6 , wherein the extracting is further based on layout information of the circuit design.

10. The method of claim 6 , wherein the extracting and the performing employ different computers for at least one of the one or more integrated circuit devices.

11. A system comprising:
one or more processors, the one or more processors programmed to:
receive failure information for one or more integrated circuit devices generated by applying test patterns to the one or more integrated circuit devices;
extract a sub-circuit from a circuit design for the one or more integrated circuit devices based on the failure information, the sub-circuit comprising one or more portions of the circuit design that include one or more defects in the one or more integrated circuit devices, wherein the extracting comprises combining fan-in cones of failing observation points and adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points, wherein the adding is performed if a size of the sub-circuit is smaller than a predetermined value;
perform fault diagnosis on the sub-circuit to generate diagnosis data based on the test patterns and the failure information; and
output the diagnosis data.

12. The system of claim 11 , wherein the one or more passing observation points are selected based on one or more relationships with the failing observation points.

13. The system of claim 11 , wherein the extracting is further based on clock information of the test patterns.

14. The system of claim 11 , wherein the extracting is further based on layout information of the circuit design.

Assignees

• Mentor Graphics Corp

Inventors

• Tang Huaxing
• Huang Yu
• Cheng Wu-Tung
• Benware Robert B
• Fan Xiaoxin

Classifications

• G06F11/26 Primary

  Functional testing · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31703 Primary

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title