Chip arrangement and method for manufacturing a chip arrangement

Patent metadata

Field	Value
Publication number	US-9856136-B2
Application number	US-201313910133-A
Country	US
Kind code	B2
Filing date	Jun 5, 2013
Priority date	Jun 5, 2013
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.

First claim

What is claimed is:

1. A chip arrangement, comprising:
a mold compound; and
a microelectromechanical systems device at least partially embedded in the mold compound where the mold compound directly contacts one or more sidewalls of the microelectromechanical systems device, the microelectromechanical systems device comprising at least one microelectromechanical systems structure at an active side of the microelectromechanical systems device and further comprising a cap disposed over a cavity where an active side of the at least one microelectromechanical systems structure faces the cap, wherein the at least one microelectromechanical systems structure comprises at least one of a sensor, an accelerometer, an oscillator, a surface acoustic wave (SAW) structure, a bulk acoustic wave (BAW) structure, or combinations thereof,
wherein the cap is disposed over at least a part of an active side of the microelectromechanical systems device so that the active side of the microelectromechanical systems device faces toward the cap, and
wherein the microelectromechanical systems device is completely enclosed.

2. The chip arrangement of claim 1 , wherein the mold compound comprises a plastic material.

3. The chip arrangement of claim 1 , wherein the mold compound comprises a resin.

4. The chip arrangement of claim 3 , wherein the resin comprises an epoxy resin.

5. The chip arrangement of claim 1 , wherein the mold compound has a first side and a second side opposite the first side, the chip arrangement further comprising:
at least one electrical connector disposed at the first side of the mold compound.

6. The chip arrangement of claim 5 , wherein the at least one electrical connector comprises at least one solder ball.

7. The chip arrangement of claim 5 , wherein the at least one electrical connector comprises a ball grid array of solder balls.

8. The chip arrangement of claim 5 , further comprising:
an interconnect structure configured to electrically couple the microelectromechanical systems to the at least one electrical connector.

9. The chip arrangement of claim 8 , wherein the interconnect structure comprises at least one through-via extending through at least a part of the microelectromechanical systems device.

10. The chip arrangement of claim 8 , wherein the interconnect structure comprises a redistribution structure disposed at the first side of the mold compound, the second side of the mold compound, or both.

11. The chip arrangement of claim 8 , wherein the interconnect structure comprises at least one through-via extending through at least a part of the mold compound.

12. The chip arrangement of claim 11 , wherein the at least one through-via extends from the first side of the mold compound to the second side of the mold compound.

13. The chip arrangement of claim 11 , wherein the at least one through-via is disposed laterally adjacent to the microelectromechanical systems device.

14. The chip arrangement of claim 1 , further comprising:
at least one semiconductor chip at least partially embedded in the mold compound.

15. The chip arrangement of claim 14 , wherein a lateral extent of the microelectromechanical systems device is less than or equal to a lateral extent of the at least one semiconductor chip.

16. The chip arrangement of claim 14 , wherein the at least one semiconductor chip is disposed laterally adjacent to the microelectromechanical systems device.

17. The chip arrangement of claim 14 , wherein the microelectromechanical systems device and the at least one semiconductor chip are arranged as a die stack.

18. The chip arrangement of claim 17 , wherein the microelectromechanical systems device is disposed laterally within a boundary of the at least one semiconductor chip.

19. The chip arrangement of claim 14 , wherein the at least one semiconductor chip comprises at least one of a logic chip, an application-specific integrated circuit, a passive device, and an active device.

20. The chip arrangement of claim 14 , further comprising:
a second interconnect structure configured to electrically couple the microelectromechanical systems device to the at least one semiconductor chip.

21. The chip arrangement of claim 20 , wherein the second interconnect structure comprises at least one through-via extending through at least a part of the microelectromechanical systems device.

22. The chip arrangement of claim 20 , wherein the mold compound has a first side and a second side opposite the first side, and wherein the second interconnect structure comprises a redistribution structure disposed at the first side of the mold compound or the second side of the mold compound, or both.

23. The chip arrangement of claim 20 , wherein the second interconnect structure comprises at least one through-via extending through at least a part of the at least one semiconductor chip.

24. The chip arrangement of claim 20 , wherein the microelectromechanical systems device and the at least one semiconductor chip are arranged as a die stack, and wherein the second interconnect structure comprises at least one conductive interconnect disposed between the at least one semiconductor chip and the microelectromechanical systems device.

25. The chip arrangement of claim 20 , wherein the second interconnect structure comprises at least one through-via extending through at least a part of the mold compound.

26. The chip arrangement of claim 14 , wherein the mold compound has a first side and a second side opposite the first side, the chip arrangement further comprising:
at least one electrical connector disposed at the first side of the mold compound; and
a third interconnect structure configured to electrically couple the at least one semiconductor chip to the at least one electrical connector.

27. The chip arrangement of claim 26 , wherein the third interconnect structure comprises a redistribution structure disposed at the first side of the mold compound.

28. The chip arrangement of claim 1 , wherein the mold compound has a first side and a second side opposite the first side, the chip arrangement further comprising:
at least one second semiconductor chip disposed over the first side of the mold compound or the second side of the mold compound, or both.

29. The chip arrangement of claim 28 , wherein the at least one second semiconductor chip is configured as a daughter die.

30. The chip arrangement of claim 28 , wherein the at least one second semiconductor chip is electrically coupled to the microelectromechanical systems device.

31. The chip arrangement of claim 1 , wherein the microelectromechanical systems device comprises at least one microelectromechanical systems structure and a metal foil configured to seal the at least one microelectromechanical systems structure.

32. The chip arrangement of claim 1 , configured as a chip package.

33. The chip arrangement of claim 1 , configured as an embedded wafer level ball grid array package.

34. The chip arrangement of claim 1 , wherein the cap comprises one or more interconnects disposed therethrough.

Assignees

• Intel Mobile Comm Gmbh
• Intel Deutschland Gmbh

Inventors

• Meyer Thorsten
• Ofner Gerald
• Mueller Christian
• Mahnkopf Reinhard
• Geissler Christian
• Augustin Andreas

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title