Method of manufacturing printed circuit board
US-2024414849-A1 · Dec 12, 2024 · US
US9854687B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9854687-B2 |
| Application number | US-201514923034-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 26, 2015 |
| Priority date | Aug 13, 2014 |
| Publication date | Dec 26, 2017 |
| Grant date | Dec 26, 2017 |
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Official abstract text for this publication.
This disclosure generally relates to high-speed fiber optic networks that use light signals to transmit data over a network. The disclosed subject matter includes devices and methods relating to header subassemblies and/or optoelectronic subassemblies. In some aspects, the disclosed devices and methods may relate to a header subassembly that can include: a multi-layer substrate with a bottom layer, a top layer having top thin film signal lines, and one or more intermediate layers having thick film traces between the top layer and the bottom layer, the thick film traces electrically coupled to the top thin film signal lines; and optoelectronic components positioned over the multi-layer substrate and electrically coupled with the signal lines.
Opening claim text (preview).
What is claimed is: 1. A header subassembly comprising: a multi-layer substrate including: a bottom layer; a top layer having top thin film signal lines; and one or more intermediate layers having thick film traces between the top layer and the bottom layer, the thick film traces being electrically coupled to the top thin film signal lines; and optoelectronic components positioned over the multi-layer substrate and electrically coupled with the top thin film signal lines; wherein at least one of the top thin film signal lines comprises: titanium (Ti) having a height of about 0.1 microns with a tolerance of 0.05 microns; palladium (Pd) having a height of about 0.2 microns with a tolerance of 0.05 microns; or gold (Au) having a height about 3 microns with a tolerance of 2 microns. 2. The header subassembly of claim 1 , wherein the top thin film signal lines have a first dimension tolerance and the thick film traces have a second dimension tolerance larger than the first dimension tolerance. 3. The header subassembly of claim 1 , wherein the top thin film signal lines have a width or a spacing smaller than a width or a spacing of the thick film traces. 4. The header subassembly of claim 1 , wherein the top thin film signal lines include one or more of: a spacing between the thin film signal lines of 0.03 millimeters with a tolerance of 0.01 millimeters; or a width of 0.03 millimeters with a tolerance of 0.02 millimeters. 5. The header subassembly of claim 1 , the optoelectronic components including one or more of: at least one receiver, at least one transmitter, a multi-channel receiver array and a multi-channel laser array, a driver, a monitor photodiode, an integrated circuit, an inductor, a capacitor, control circuitry, a lens, a prism, a mirror, or a filter. 6. The header subassembly of claim 1 , wherein at least one of the top thin film signal lines is an RF line. 7. The header subassembly of claim 1 , further comprising contact pads on the bottom layer, the contact pads electrically coupled to vias extending through at least a portion of the multi-layer substrate, the vias electrically coupled to the top thin film signal lines. 8. A header subassembly comprising: a multi-layer substrate including: a bottom layer; a top layer having top thin film signal lines; and one or more intermediate layers having thick film traces between the top layer and the bottom layer, the thick film traces being electrically coupled to the top thin film signal lines; and optoelectronic components positioned over the multi-layer substrate and electrically coupled with the top thin film signal lines; wherein the thin film signal lines include a spacing between the thin film signal lines of 0.03 millimeters with a tolerance of 0.01 millimeters. 9. A header subassembly comprising: a multi-layer substrate including: a bottom layer; a top layer having top thin film signal lines; and one or more intermediate layers having thick film traces between the top layer and the bottom layer, the thick film traces being electrically coupled to the top thin film signal lines; and optoelectronic components positioned over the multi-layer substrate and electrically coupled with the top thin film signal lines; wherein at least one of the thin film signal lines includes a width of about 0.03 millimeters with a tolerance of 0.02 millimeters.
Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title
with surface mounted components (H05K3/32 takes precedence) · CPC title
Varying width along a single conductor; Conductors or pads having different widths · CPC title
Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads · CPC title
Varying thickness of a single conductor; Conductors in the same plane having different thicknesses · CPC title
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