Automatic detection of change in PLL locking trend

Patent metadata

Field	Value
Publication number	US-9853807-B2
Application number	US-201615135212-A
Country	US
Kind code	B2
Filing date	Apr 21, 2016
Priority date	Apr 21, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

First claim

What is claimed is:

1. A phase lock loop (PLL) controller, comprising:
a clock generator configured to:
receive an error signal from a PLL, the error signal representing a difference between a frequency or a phase of a reference input signal of the PLL and a frequency or a phase of an output signal of the PLL, and
generate a clock signal based on the error signal;

a trend detector configured to:
sample the error signal in accordance with the clock signal, and
determine a trend of the sampled error signal; and

a trend change detector configured to:
compare the trend of the sampled error signal to a previous trend of the sampled error signal to detect for a change in the trend of the sampled error signal, and
initiate a change in a mode of operation of the PLL upon detecting the change in the trend of the sampled error signal.

2. The PLL controller of claim 1 , wherein the clock generator is further configured to collect a plurality of samples of the output signal and to switch logical levels of the clock signal in response to changes between the plurality of samples to generate the clock signal.

3. The PLL controller of claim 1 , wherein the trend of the sampled error signal, comprises:
a positive trend;
a negative trend; or
a flat trend.

4. The PLL controller of claim 1 , wherein the PLL comprises:
an all digital PLL (ADPLL).

5. The PLL controller of claim 1 , wherein the reference input signal and the output signal comprise a digital reference input signal and a digital output signal, respectively.

6. The PLL controller of claim 1 , wherein the reference input signal represents a digital representation of a first time-varying signal having a first frequency and a first phase,
wherein the output signal represents a digital representation of a second time-varying signal having a second frequency and a second phase,
wherein the PLL is configured to adjust the second frequency to be proportional to the first frequency in a frequency tracking mode of operation and to change to a phase tracking mode of operation in response to the change in the mode of operation of the PLL to adjust the second phase to be proportional to the first phase.

7. The PLL controller of claim 1 , wherein the trend detector is configured to:
sample the error signal to provide a plurality of samples of the error signal, and
compare a first sample from among the plurality of samples and a second sample from among the plurality of samples to determine a second trend of the sampled error signal.

8. The PLL controller of claim 7 , wherein the trend detector is configured to initiate the change in the mode of operation of the PLL when the trend of the sampled error signal differs from the second trend of the sampled error signal.

9. The PLL controller of claim 7 , wherein the trend detector is configured not to initiate the change in the mode of operation of the PLL when the trend of the sampled error signal is similar to the second trend of the sampled error signal.

10. An all-digital phase lock loop (ADPLL), comprising:
a phase frequency detector (PFD) configured to compare a first frequency of a first time-varying signal represented by a digital reference input signal and a second frequency of a second time-varying signal represented by a digital output signal to provide a frequency error component of an error signal;
a time-to-digital converter (TDC) configured to compare a first phase of the first time-varying signal and a second phase of the second time-varying signal to provide a phase error component of the error signal;
a digital controlled oscillator (DCO) configured to adjust the second frequency and the second phase based upon the error signal; and
a controller configured to:
monitor the error signal to detect for a change in a trend of the error signal, and
disable or enable the TDC upon detecting the change in the trend of the error signal.

11. The ADPLL of claim 10 , wherein the PFD comprises:
a DCO accumulator configured to accumulate the digital reference input signal and the digital output signal to provide a digital output value;
a reference accumulator configured to accumulate the digital reference input signal and a digital data signal to provide a digital reference input value; and
a digital combination network configured to determine a difference between the digital output value and the digital reference input value to provide the frequency component of the error signal.

12. The ADPLL of claim 11 , wherein the digital data signal is a digital representation of a third time-varying signal having a third frequency that is proportional to the second frequency.

13. The ADPLL of claim 12 , wherein the second frequency and the third frequency are similar frequencies.

14. The ADPLL of claim 11 , wherein the controller is configured to:
determine the trend of the error signal;
compare the trend of the error signal to a previous trend of the error signal to detect the change in the trend of the error signal, and
disable or enable the TDC upon detecting the change in the trend of the error signal.

15. A method for operating a phase lock loop (PLL), the method comprising
receiving a first error signal from the PLL in a frequency tracking mode of operation, the first error signal representing a difference between a frequency of a reference input signal of the PLL and a frequency of an output signal of the PLL;
sampling the first error signal;
determining a trend of the sampled first error signal;
comparing the trend of the sampled first error signal to a previous trend of the sampled first error signal to detect for a change in the trend of the sampled first error signal;
initiating a change in a mode of operation of the PLL from the frequency tracking mode of operation to a phase tracking mode of operation upon detecting the change in the trend of the sampled first error signal; and
receiving a second error signal from the PLL in the phase tracking mode of operation, the second error signal representing a difference between a phase of the reference input signal and a phase of the output signal.

16. The method of claim 15 , wherein the trend comprises:
a positive trend;
a negative trend; or
a flat trend.

17. The method of claim 15 , wherein the reference input signal represents a digital representation of a first time-varying signal having a first frequency and a first phase,
wherein the output signal represents a digital representation of a second time-varying signal having a second frequency and a second phase,
wherein the first error signal represents a difference between the first frequency and the second frequency, and
wherein the second error signal represents a difference between the first phase and the second phase.

18. The method of claim 15 , wherein the sampling comprises:
sampling the first error signal to provide a plurality of samples of the first error signal, and wherein the determining comprises:
comparing a first sample from among the plurality of samples and a second sample from among the plurality of samples to determine a second trend of the sampled first error signal.

19. The method of claim 18 , wherein the initiating comprises:
initiating the change in the mode of operation of the PLL when the trend of the sampled first error signal differs from the second trend of the sampled first error signal.

20. The method of claim 18 , wherein the initiating comprises:
not initiating the change in the mode of operation of the PLL when the trend of the sa

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Tsung-Hsien
• Chang Chih-Hsien

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0994 Primary

  comprising an accumulator · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title