Phase locked loop

Patent metadata

Field	Value
Publication number	US-9257998-B2
Application number	US-201314050691-A
Country	US
Kind code	B2
Filing date	Oct 10, 2013
Priority date	Oct 10, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A circuit includes a phase locked loop and a logic IC. The phase locked loop is coupled to the logic IC. The logic IC is configured for generating an adaptive residue according to a first parameter and a second parameter. The phase locked loop is configured for providing the first parameter and the second parameter, and the phase locked loop generates an oscillator signal based on the adaptive residue.

First claim

What is claimed is:

1. A circuit, comprising:
a phase locked loop comprising a phase detector, a digital filter, and a digital control oscillator, the phase locked loop configured for providing a first parameter being related to a period of the phase detector and a period of the digital control oscillator and a second parameter being related to a frequency of the digital control oscillator and a frequency of a reference signal, the phase locked loop generating an oscillator signal based on an adaptive residue; and
a logic integrated circuit (IC) coupled to the phase locked loop and configured for using the first parameter, a bit number utilized by the phase locked loop, the second parameter, and a residue generated from an inverter of the phase detector, to generate the adaptive residue.

2. The circuit according to claim 1 , wherein
the digital filter is coupled to the phase detector, and
the digital control oscillator is coupled to the digital filter.

3. The circuit according to claim 2 , wherein the first parameter and the second parameter are determined as follows:

K
TDC

=

Δ
⁢

⁢

T

TDC
,
res

T
V

,

⁢
and

nK
DCO

=

f
R

Δ
⁢

⁢

f
V

,

where K TDC is the first parameter, ΔT TDC,res is the period of the phase detector, T V is the period of the digital control oscillator, nK DCO is the second parameter, f R is the frequency of the reference signal, and Δf V is the frequency of the digital control oscillator.

4. The circuit according to claim 3 , wherein the logic IC comprises:
a first multiplier coupled to the phase detector, the first multiplier configured for multiplying the first parameter and the bit number utilized by the phase locked loop to generate a first calculated value;
a calculation logic gate coupled to the digital control oscillator, the calculation logic gate configured for using the second parameter and a third parameter generated according to the digital filter to generate a second calculated value;
an adder coupled to the calculation logic gate, the adder configured for adding the second calculated value and the residue generated from the inverter of the phase detector to generate a third calculated value; and
a second multiplier coupled to the first multiplier and the adder, the second multiplier configured for multiplying the first calculated value and the third calculated value to generate the adaptive residue.

5. The circuit according to claim 4 , wherein the adaptive residue is determined as follows:

Residue
=

K
TDC

×

2

BIT
fraction

×

(

INV
number

+
ϕ

)

,

⁢
and

ϕ
=

ABS
⁡

[

1
-

1

nK
DCO

×
2
×
α

]

,

where Residue is the adaptive residue, BIT fraction is the bit number utilized by the phase locked loop, INV number is the residue generated from the inverter of the phase detector, and α is a parameter of the digital filter.

6. A circuit, comprising:
a digital control oscillator configured for generating a first oscillator signal based on an initial residue signal;
a phase detector coupled to the digital control oscillator, the phase detector configured for comparing the first oscillator signal with a reference signal to generate the initial residue signal; and
a digital filter coupled to the phase detector, the digital filter configured for modifying the initial residue signal based on an adaptive residue related to a first parameter, a second parameter, a bit number and a residue, to generate a modified residue signal, wherein the first parameter is related to a period of the phase detector and a period of the digital control oscillator, the bit number is utilized by a phase locked loop comprising the digital control oscillator, the phase detector and the digital filter, the second parameter is related to a frequency of the digital control oscillator and a frequency of a reference signal, and the residue is generated from an inverter of the phase detector, wherein the digital control oscillator is configured for generating a second oscillator signal base on the modified residue signal.

7. The circuit according to claim 6 , wherein the first parameter is determined as follows:

K
TDC

=

Δ
⁢

⁢

T

TDC
,
res

T
V

,

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Tsung-Hsien

Classifications

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title