Method and apparatus of frequency synthesis

Patent metadata

Field	Value
Publication number	US-9853650-B1
Application number	US-201615356796-A
Country	US
Kind code	B1
Filing date	Nov 21, 2016
Priority date	Nov 21, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An apparatus having a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal, an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal, a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal, a controllable oscillator configured to receive the oscillator control signal and output a fifth clock, a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor, a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor, a digital phase detector configured to receive the third clock and the fourth clock and output a digital timing error signal, wherein the digital phase detector is self-calibrated so that a mean value of the digital timing error signal is zero, and a correlation circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.

First claim

What is claimed is:

1. An apparatus comprising:
a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal;
an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal;
a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal;
a controllable oscillator configured to receive the oscillator control signal and output a fifth clock;
a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor;
a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor;
a digital phase detector configured to receive the third clock and the fourth clock and output a digital timing error signal, wherein the digital phase detector is self-calibrated so that a mean value of the digital timing error signal is zero; and
a correlation circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.

2. The apparatus of claim 1 , wherein a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a timing offset.

3. The apparatus of claim 1 , wherein the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal.

4. The apparatus of claim 3 , wherein a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal.

5. The apparatus of claim 3 , wherein the digitally controlled variable delay circuit comprises: a tunable inverter comprising an inverter supplied by a rail voltage controlled by the gain control signal, and a variable capacitor controlled by the noise cancellation signal.

6. The apparatus of claim 1 , wherein the digital phase detector comprises: a skew adjustment circuit configured to receive the third clock and the fourth clock and output a first delayed clock and a second delayed clock in accordance with a delay control signal, a time-to-digital converter configured to receive the first delayed clock and the second delay clock and output the digital timing error signal, and an integrator configured to receive the digital timing error signal and output the delay control signal.

7. The apparatus of claim 1 , wherein the correlation circuit comprises a digital signal processing unit configured to decrement the gain control signal by a value determined by the digital timing error signal if the noise cancellation signal is positive, increment the gain control signal by the value determined by the digital timing error signal if the noise cancellation signal is negative, or make no change to the gain control signal if the noise cancellation signal is zero.

8. The apparatus of claim 1 , wherein the analog phase detector comprises a phase/frequency detector.

9. The apparatus of claim 1 , wherein the controllable oscillator is a voltage-controlled oscillator.

10. The apparatus of claim 1 , wherein the clock divider is a counter.

11. A method comprising:
receiving a first clock and a clock multiplication factor;
modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor;
establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor;
deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with a noise cancellation signal and a gain control signal;
establishing analog timing error signal by detecting a timing difference between the fourth clock and the third clock using an analog phase detector;
filtering the analog timing error signal into an oscillator control signal using a filtering circuit;
outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator;
outputting the second clock by dividing down the fifth clock in accordance with the division factor;
establishing a digital timing error signal by detecting the timing difference between the fourth clock and the third clock using a digital phase detector that is self-calibrating so that a mean value of the digital timing error signal is zero; and
adjusting the gain control signal in accordance with a correlation between the digital timing error signal and the noise cancellation signal.

12. The method of claim 11 , wherein a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a timing offset.

13. The method of claim 11 , wherein the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal.

14. The method of claim 13 , wherein a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal.

15. The method of claim 13 , wherein the digitally controlled variable delay circuit comprises: a tunable inverter comprising an inverter supplied by a rail voltage controlled by the gain control signal, and a variable capacitor controlled by the noise cancellation signal.

16. The method of claim 11 , wherein the digital phase detector comprises: a skew adjustment circuit configured to receive the third clock and the fourth clock and output a first delayed clock and a second delayed clock in accordance with a delay control signal, a time-to-digital converter configured to receive the first delayed clock and the second delay clock and output the digital timing error signal, and an integrator configured to receive the digital timing error signal and output the delay control signal.

17. The method of claim 11 , wherein the correlation operation is performed by a correlation circuit that comprises a digital signal processing unit configured to decrement the gain control signal by a value determined by the digital timing error signal if the noise cancellation signal is positive, increment the gain control signal by the value determined by the digital timing error signal if the noise cancellation signal is negative, or make no change to the gain control signal if the noise cancellation signal is zero.

18. The method of claim 11 , wherein the analog phase detector comprises a phase/frequency detector.

19. The method of claim 11 , wherein the controllable oscillator is a voltage-controlled osc

Assignees

• Realtek Semiconductor Corp

Inventors

• Kuan Chi-Kung
• Zhao Yu
• Lin Chia-Liang (Leon)

Classifications

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03L7/235

  Nested phase locked loops · CPC title