Self-calibrating fractional-N phase lock loop and method thereof

Patent metadata

Field	Value
Publication number	US-9705512-B1
Application number	US-201615271182-A
Country	US
Kind code	B1
Filing date	Sep 20, 2016
Priority date	Sep 20, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise and an output of the timing detection circuit.

First claim

What is claimed is:

1. A circuit comprising:
a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal;
a timing detection circuit configured to receive the third clock and the fourth clock and output a timing error signal;
a filtering circuit configure to receive the timing error signal and output an oscillator control signal;
a controllable oscillator configured to receive the oscillator control signal and output a fifth clock;
a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor;
a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor; and
a calibration circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.

2. The circuit of claim 1 , wherein a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a fixed timing offset.

3. The circuit of claim 1 , wherein the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal.

4. The circuit of claim 3 , wherein a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal.

5. The circuit of claim 4 , wherein the calibration circuit comprises a charge pump configured to receive the timing error signal and output an intermediate current signal in accordance with a common-mode feedback voltage, a single-pole-double-throw switch controlled by a sign of the noise cancellation signal, an integrator configured to receive the intermediate current signal via the single-pole-double-throw switch and output the gain control signal, and a common-mode feedback network configured to receive a first voltage at a positive input terminal and a second voltage at a negative input terminal of the integrator and output the common mode feedback voltage, wherein: a first throw of the single-pole-double-throw switch couples to the positive input terminal of the integrator, and a second throw of the single-pole-double-throw switch couples to the negative input terminal of the integrator.

6. The circuit of claim 5 , wherein the integrator comprises a differential operational amplifier and two feedback capacitors.

7. The circuit of claim 6 , wherein the single-pole double-throw switch is configured to steer the intermediate current to the positive input terminal of the integrator when the noise cancellation signal is of a first sign, and steer the intermediate current to the negative input terminal of the integrator when the noise cancellation signal is of a second sign.

8. The circuit of claim 1 , wherein the modulator comprises a first order delta-sigma modulator.

9. The circuit of claim 1 , wherein the controllable oscillator is a voltage-controlled oscillator.

10. The circuit of claim 1 , wherein the clock divider is a counter.

11. A method comprising:
receiving a first clock and a clock multiplication factor;
modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor;
establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor;
deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with the noise cancellation signal and a gain control signal;
establishing a timing error signal by detecting a timing difference between the fourth clock and the third clock;
filtering the timing error signal into an oscillator control signal;
outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator;
outputting the second clock by dividing down the fifth clock in accordance with the division factor; and
adjusting the gain control signal in accordance with a correlation between the timing error signal and the noise cancellation signal.

12. The method of claim 11 , wherein the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal.

13. The method of claim 12 , wherein a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal.

14. The method of claim 11 , wherein adjusting the gain control signal in accordance with a correlation between the timing error signal and the noise cancellation signal the calibration circuit comprises using a calibration circuit comprising: a charge pump configured to receive the timing error signal and output an intermediate current signal in accordance with a common-mode feedback voltage, a single-pole-double-throw switch controlled by a sign of the noise cancellation signal, an integrator configured to receive the intermediate current signal via the single-pole-double-throw switch and output the gain control signal, and a common-mode feedback network configured to receive a first voltage at a positive input terminal and a second voltage at a negative input terminal of the integrator and output the common mode feedback voltage, wherein: a first throw of the single-pole-double-throw switch couples to the positive input terminal of the integrator, and a second throw of the single-pole-double-throw switch couples to the negative input terminal of the integrator.

15. The method of claim 14 , wherein the integrator comprises a differential operational amplifier and two feedback capacitors.

16. The method of claim 15 , wherein the single-pole double-throw switch is configured to steer the intermediate current to the positive input terminal of the integrator when the noise cancellation signal is of a first sign, and steer the intermediate current to the negative input terminal of the integrator when the noise cancellation signal is of a second sign.

17. The method of claim 11 , wherein modulating the clock multiplication factor into the division factor comprises using a first order delta-sigma modulator.

18. The method of claim 11 , wherein the controllable oscillator is a voltage controlled oscillator.

Assignees

• Realtek Semiconductor Corp

Inventors

• Kuan Chi-Kung
• Zhao Yu
• Lin Chia-Liang

Classifications

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/1974

  for fractional frequency division · CPC title

• H03L7/0898 Primary

  the source or sink current values being variable (H03L7/0896 takes precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title