Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9853160-B2
Application number	US-201615135566-A
Country	US
Kind code	B2
Filing date	Apr 22, 2016
Priority date	May 26, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including an active region defined by a device isolation layer;
a fin pattern on the active region and extending in a first direction, the fin pattern comprising a gate fin region and a source/drain fin region;
a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction; and
a source/drain portion provided on a sidewall of the source/drain fin region,
wherein, when measured in the second direction, a width of the source/drain fin region at a height is different from a width of the gate fin region at the height,
wherein the source/drain fin region is a portion of the substrate.

2. The semiconductor device of claim 1 , wherein the width of the source/drain fin region is less than the width of the gate fin region.

3. The semiconductor device of claim 2 , wherein a width of an upper portion of the source/drain fin region is less than a width of a lower portion of the source/drain fin region.

4. The semiconductor device of claim 1 , wherein the gate fin region has a top surface that is positioned at substantially the same level as a top surface of the source/drain fin region.

5. The semiconductor device of claim 1 , wherein the gate fin region has a top surface that is positioned at a level different from a top surface of the source/drain fin region.

6. The semiconductor device of claim 5 , wherein the top surface of the source/drain fin region is positioned at a level lower than the top surface of the gate fin region.

7. The semiconductor device of claim 1 , wherein the source/drain portion is an epitaxial pattern.

8. The semiconductor device of claim 1 , wherein the source/drain portion is a conductive pattern.

9. The semiconductor device of claim 1 ,
wherein the height is a middle height between an upper surface of the device isolation layer and a top surface of the gate fin region,
wherein a distance between an upper surface of the device isolation layer and the middle height is equal to a distance between the middle height and a top surface of the gate fin region.

10. The semiconductor device of claim 1 , wherein opposite sidewalls of the source/drain fin region include at least a portion having a slanted profile.

11. The semiconductor device of claim 1 , further comprising:
an insulating pattern between the substrate and the gate pattern;
a spacer provided on a sidewall of the gate pattern; and
an interlayer insulating layer provided on the substrate to cover the source/drain portion.

12. A semiconductor device, comprising:
a substrate including an active region defined by a device isolation layer;
a fin pattern on the active region and extending in a first direction, the fin pattern comprising a gate fin region and a source/drain fin region;
a gate pattern provided on the gate fin region to extend in a second direction crossing the first direction; and
a source/drain portion provided on a sidewall of the source/drain fin region,
wherein when measured in the second direction, a width of source/drain fin region is less than a width of the active region,
wherein the source/drain fin region is a portion of the substrate.

13. The semiconductor device of claim 12 , wherein the source/drain portion is a conductive pattern.

14. The semiconductor device of claim 12 ,
wherein, when measured in the second direction, the width of the source/drain fin region is less than a width of the gate fin region.

15. The semiconductor device of claim 14 , wherein the width of the active region is the same as the width of the gate fin region.

16. The semiconductor device of claim 12 ,
wherein the width of the source/drain fin region corresponds to a width of the source/drain fin region at a height,
wherein the width of the gate fin region corresponds to a width of the gate fin region at the height,
wherein the height is a middle height between an upper surface of the device isolation layer and a top surface of the gate fin region, and
wherein a distance between the upper surface of the device isolation layer and the middle height is equal to a distance between the middle height and the top surface of the gate fin region.

17. The semiconductor device of claim 12 , wherein the source/drain portion is a conductive pattern.

18. A semiconductor device, comprising:
a substrate including an active region defined by a device isolation layer;
a fin pattern on the active region and extending in a first direction, the fin pattern comprising a gate fin region and a source/drain fin region;
a gate pattern provided on the gate fin region to extend in a second direction crossing the first direction; and
a source/drain portion provided on a sidewall of the source/drain fin region,
wherein when measured in the second direction, a width of source/drain fin region is less than a width of the gate fin region, and a top surface of the source/drain fin region is positioned at a lower level than that of the gate fin region,
wherein a sidewall of the source/drain fin region includes a slanted portion, and
wherein the source/drain fin region is a portion of the substrate.

19. The semiconductor device of claim 18 ,
wherein the width of the source/drain fin region corresponds to a width of the source/drain fin region at a height,
wherein the width of the gate fin region corresponds to a width of the gate fin region at the height,
wherein the height is a middle height between an upper surface of the device isolation layer and a top surface of the gate fin region, and
wherein a distance between the upper surface of the device isolation layer and the middle height is equal to a distance between the middle height and the top surface of the gate fin region.

20. The semiconductor device of claim 18 , wherein the source/drain portion is an epitaxial pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Sujin
• Kim Jinbum
• Moon Kang Hun
• Lee Kwan Heum
• Lee Byeongchan
• Lee Choeun
• Xu Yang

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6211 Primary

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/7851 Primary

  Electricity · mapped topic