Semiconductor device and method of formation

Patent metadata

Field	Value
Publication number	US-9853105-B2
Application number	US-201615381047-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	Aug 11, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first source/drain region over the substrate;
a second source/drain region over the substrate;
a graphene channel between the first source/drain region and the second source/drain region; and
a gate, wherein:
a first surface of the first source/drain region interfaces with the graphene channel,
a second surface of the first source/drain region faces the gate, the second surface of the first source/drain region opposite the first surface of the first source/drain region, and
a third surface of the first source/drain region faces the gate.

2. The semiconductor device of claim 1 , wherein the gate extends around the first source/drain region from a first side of the graphene channel to a second side of the graphene channel opposite the first side.

3. The semiconductor device of claim 1 , comprising a dielectric layer underlying the first source/drain region, the graphene channel, and the gate.

4. The semiconductor device of claim 3 , wherein the dielectric layer overlies the substrate.

5. The semiconductor device of claim 1 , comprising a dielectric layer over the substrate, wherein the dielectric layer is in contact with the first source/drain region, the graphene channel, and the gate.

6. The semiconductor device of claim 5 , wherein the dielectric layer is in contact with the second source/drain region.

7. The semiconductor device of claim 1 , comprising a second gate under the substrate.

8. The semiconductor device of claim 1 , wherein a top surface of the first source/drain region, a top surface of the graphene channel, and a top surface of the gate are co-planar.

9. The semiconductor device of claim 1 , wherein the first source/drain region comprises graphene.

10. The semiconductor device of claim 9 , wherein the gate comprises graphene.

11. The semiconductor device of claim 1 , wherein the gate comprises graphene.

12. The semiconductor device of claim 1 , wherein a top surface of the substrate lies in a first plane, a bottom surface of the gate lies in a second plane parallel to the first plane, and a bottom surface of the graphene channel lies in the second plane.

13. A semiconductor device, comprising:
a substrate;
a first source/drain region over the substrate;
a second source/drain region over the substrate;
a graphene channel between the first source/drain region and the second source/drain region; and
a gate, wherein:
a first surface of the first source/drain region interfaces with the graphene channel,
a second surface of the first source/drain region faces the gate, the second surface of the first source/drain region opposite the first surface of the first source/drain region, and
the gate extends around the first source/drain region from a first side of the graphene channel to a second side of the graphene channel opposite the first side.

14. The semiconductor device of claim 13 , comprising a dielectric layer underlying the first source/drain region, the graphene channel, and the gate.

15. The semiconductor device of claim 14 , wherein the dielectric layer overlies the substrate.

16. The semiconductor device of claim 13 , comprising a second gate under the substrate.

17. The semiconductor device of claim 13 , wherein the gate comprises graphene.

18. The semiconductor device of claim 17 , wherein the first source/drain region comprises graphene.

19. A semiconductor device, comprising:
a substrate;
a first source/drain region over the substrate;
a second source/drain region over the substrate;
a graphene channel between the first source/drain region and the second source/drain region; and
a gate, wherein:
a first surface of the first source/drain region interfaces with the graphene channel,
a second surface of the first source/drain region faces the gate, the second surface of the first source/drain region opposite the first surface of the first source/drain region, and
a top surface of the first source/drain region, a top surface of the graphene channel, and a top surface of the gate are co-planar.

20. The semiconductor device of claim 19 , wherein the gate comprises grapheme.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Lin Meng-Yu
• Lin Shih-Yen
• Lee Si-Chen

Classifications

• H01L29/66015

  Electricity · mapped topic

• H01L2924/13088

  Electricity · mapped topic

• H01L29/78603

  Electricity · mapped topic

• H01L29/1606 Primary

  Electricity · mapped topic

• H01L29/42384

  Electricity · mapped topic