Thin film transistor array substrate

US9853067B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9853067-B2
Application numberUS-201314137861-A
CountryUS
Kind codeB2
Filing dateDec 20, 2013
Priority dateDec 24, 2012
Publication dateDec 26, 2017
Grant dateDec 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A thin film transistor array substrate includes a substrate, a plurality of pixel elements arranged on the substrate, each of the pixel elements including a thin film transistor and a pixel electrode electrically connected with the thin film transistor, a light shielding electrode disposed between the substrate and the thin film transistor to shield a channel of the thin film transistor, and a storage capacitor including a first electrode and a second electrode disposed opposite to each other. The light shielding electrode includes a transparent electrically-conductive layer and a non-transparent electrically-conductive layer stacked on top of each other. The first electrode of the storage capacitor is disposed in a same layer and of a same material as the transparent electrically-conductive layer of the light shielding electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A thin film transistor array substrate, comprising: a substrate; a plurality of pixel elements arranged on the substrate, each of the pixel elements comprising a thin film transistor and a pixel electrode electrically connected with a drain/source of the thin film transistor; a light shielding electrode disposed between the substrate and the thin film transistor and configured to shield a channel of the thin film transistor; wherein the light shielding electrode comprises a transparent electrically-conductive layer and a non-transparent electrically-conductive layer stacked on top of each other; a storage capacitor comprising a first electrode and a second electrode disposed opposite to each other, the [A&B1] first electrode of the storage capacitor being located in a same layer as the transparent electrically-conductive layer of the light shielding electrode, wherein the first electrode of the storage capacitor is formed of transparent electrically-conductive material; a common electrode; wherein a potential of the first electrode is the same as a potential of the common electrode; and a peripheral drive circuit, comprising a peripheral transparent electrically-conductive layer, a first connection metal, a second connection metal, wherein the first connection metal and the common electrode are electrically connected and have the same potential, wherein the second connection metal and the first connection metal are electrically connected, wherein the second connection metal and the peripheral transparent electrically-conductive layer are electrically connected, wherein the peripheral transparent electrically-conductive layer and the first electrode of the storage capacitor are electrically connected, and wherein the peripheral drive circuit provides a potential to the first electrode of the storage capacitor. 2. The thin film transistor array substrate according to claim 1 , wherein the first electrode of the storage capacitor is formed by a same material as the transparent electrically-conductive layer of the light shielding electrode. 3. The thin film transistor array substrate according to claim 2 , further comprises: a first insulation layer on the light shielding electrode and the first electrode of the storage capacitor; an active layer on the first insulation layer and the light shielding electrode; a second insulation layer on the active layer; and a source electrode and a drain electrode on the second insulation layer and electrically connected with the active layer each through a via traversing the second insulation layer. 4. The thin film transistor array substrate according to claim 3 , wherein the second electrode of the storage capacitor is disposed in a same layer and of a same material as the source electrode and the drain electrode. 5. The thin film transistor array substrate according to claim 3 , wherein the second electrode of the storage capacitor is disposed in a same layer and of a same material as the active layer. 6. The thin film transistor array substrate according to claim 3 , wherein the thin film transistor further comprises a top gate disposed above the channel. 7. The thin film transistor array substrate according to claim 6 , wherein the second electrode of the storage capacitor is disposed in a same layer and of a same material as the top gate. 8. The thin film transistor array substrate according to claim 3 , wherein the light shielding electrode is a bottom gate of the thin film transistor. 9. The thin film transistor array substrate according to claim 3 , the active layer is electrically connected with the source electrode and the drain electrode through the vias in the second insulating layer and a conductive etching stopper layer. 10. A display panel, comprising the thin film transistor array substrate according to claim 1 .

Assignees

Inventors

Classifications

  • Arrangements for improving the aperture ratio · CPC title

  • Storage capacitors associated with the pixel electrode · CPC title

  • Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9853067B2 cover?
A thin film transistor array substrate includes a substrate, a plurality of pixel elements arranged on the substrate, each of the pixel elements including a thin film transistor and a pixel electrode electrically connected with the thin film transistor, a light shielding electrode disposed between the substrate and the thin film transistor to shield a channel of the thin film transistor, and a …
Who is the assignee on this patent?
Shanghai Tianma Microelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/1255. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).