Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9853029-B2
Application number	US-201615058696-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Jun 23, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An integrated circuit (IC) device includes a first-fin-type active region, a second-fin-type active region, and an inter-region stepped portion. The first-fin-type active region protrudes from a substrate in a first region of the substrate and has a first width in a first direction. The second-fin-type active region protrudes from the substrate in a second region of the substrate and has a second width in the first direction. The second width is less than the first width. The inter-region stepped portion is formed at an interface between the first region and the second region on a bottom surface, which is a portion of the substrate between the first-fin-type active region and the second-fin-type active region.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising:
a first-fin-type active region protruding in a height direction from a substrate in a first region of the substrate, the first-fin-type active region having a first width in a first direction different from the height direction;
a second-fin-type active region protruding in the height direction from the substrate in a second region of the substrate, the second-fin-type active region having a second width in the first direction, wherein the second width is less than the first width; and
an inter-region stepped portion at an interface between the first region and the second region on a bottom surface, which is a portion of the substrate that continuously extends from the first-fin-type active region to the second-fin-type active region.

2. The IC device of claim 1 , wherein the first-fin-type active region has a channel region of a different conductivity type from a channel region of the second-fin-type active region.

3. The IC device of claim 1 , wherein the first region comprises an NMOS transistor region, and the second region comprises a PMOS transistor region.

4. The IC device of claim 1 , wherein the inter-region stepped portion, the first-fin-type active region, and the second-fin-type active region extend parallel to one another.

5. The IC device of claim 1 , wherein the bottom surface comprises a first bottom unit at a first level in the first region on the substrate and a second bottom unit at a second level in the second region on the substrate, wherein the second level is different from the first level, and
the inter-region stepped portion extends along an interface between the first bottom unit and the second bottom unit.

6. The IC device of claim 1 , wherein a first distance from the inter-region stepped portion to the first-fin-type active region in the first direction is different from a second distance from the inter-region stepped portion to the second-fin-type active region in the first direction.

7. The IC device of claim 1 , wherein the first region comprises an NMOS transistor region, and the second region comprises a PMOS transistor region, and
a first distance from the inter-region stepped portion to the first-fin-type active region in the first direction is greater than a second distance from the inter-region stepped portion to the second-fin-type active region.

8. The IC device of claim 1 , wherein a lowest portion of the second-fin-type active region is located at a lower level than a lowest portion of the first-fin-type active region on the substrate.

9. An integrated circuit (IC) device comprising:
a substrate having a first region and a second region adjacent to each other;
a plurality of first-fin-type active regions protruding in a height direction from the substrate in the first region and extending parallel to one another;
a plurality of second-fin-type active regions protruding in the height direction from the substrate in the second region and extending parallel to one another, each second-fin-type active region having a smaller width than a width of any one of the plurality of first-fin-type active regions in a first direction that is different from the height direction; and
an inter-region isolation region having an inter-region stepped portion at an interface between the first region and the second region on a bottom surface of the substrate that continuously extends from the plurality of first-fin-type active regions to the plurality of second-fin-type active regions.

10. The IC device of claim 9 , wherein the plurality of first-fin-type active regions and the plurality of second-fin-type active regions extend parallel to one another such that the inter-region stepped portion is between the plurality of first-fin-type active regions and the plurality of second-fin-type active regions, and
the plurality of first-fin-type active regions and the plurality of second-fin-type active regions are at a uniform pitch in the first direction.

11. The IC device of claim 9 , wherein the plurality of first-fin-type active regions and the plurality of second-fin-type active regions extend parallel to one another such that the inter-region stepped portion is between the plurality of first-fin-type active regions and the plurality of second-fin-type active regions, and
a width of the inter-region isolation region is greater than a first space between adjacent ones of the plurality of first-fin-type active regions and greater than a second space between adjacent ones of the plurality of second-fin-type active regions in the first direction.

12. The IC device of claim 9 , wherein a first distance from the inter-region stepped portion to the plurality of first-fin-type active regions is greater than a second distance from the inter-region stepped portion to the plurality of second-fin-type active regions.

13. An integrated circuit (IC) device comprising:
first and second fin-type active regions protruding from adjacent first and second surfaces of a substrate, respectively, wherein the first and second fin-type active regions differ in width;
a first stressor liner on the first fin-type active region that imparts a tensile stress thereon; and
a second stressor liner on the second fin-type active region that imparts a compressive stress thereon,
wherein the first and second surfaces of the substrate are non-coplanar and define an inter-region stepped portion in the substrate at an interface between the first surface and the second surface, and wherein an interface between the first and second stressor liners is aligned with the inter-region stepped portion in the substrate.

14. The device of claim 13 , wherein the inter-region stepped portion in the substrate extends between the first and second fin-type active regions, and wherein the second fin-type active region is closer to the inter-region stepped portion than the first fin-type active region.

15. The device of claim 14 , wherein the first and second fin-type active regions comprise different conductivity types and/or different materials.

16. The device of claim 15 , further comprising first and second buried insulating layers on the first and second stressor liners, respectively, wherein an interface between the first and second buried insulating layers is aligned with the inter-region stepped portion in the substrate.

17. The device of claim 16 , wherein the first and second fin-type active regions extend parallel to the inter-region stepped portion, and further comprising:
a first gate line structure on the first fin-type active region; and
a second gate line structure different from the first gate line structure on the second fin-type active region,
wherein an interface between the first and second gate line structures is aligned with the inter-region stepped portion of the substrate.

18. The device of claim 16 , wherein the first and second fin-type active regions extend perpendicular to the inter-region stepped portion and further comprising:
a first gate line structure on the first fin-type active region extending parallel to the inter-region stepped portion; and
a second gate line structure different from the first gate line structure on the second fin-type active region extending parallel to the inter-region stepped portion,
wherein the inter-region stepped portion extends between the first and second gate line structures.

19. The device of claim 16 , wherein:
the first fin-type active region is one of a plurality of first fin-type active regions protruding from and

Assignees

• You Jung-Gun
• Park Gi-Gwan
• Samsung Electronics Co Ltd

Inventors

• You Jung-Gun
• Park Gi-Gwan

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H01L21/845

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L21/28008

  Electricity · mapped topic