Electronic component, electronic apparatus, and method of manufacturing electronic apparatus

Patent metadata

Field	Value
Publication number	US-9853014-B2
Application number	US-201615275752-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Oct 1, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface; a second portion configured to be formed inside the first portion, and have second thermal conductivity lower than the first thermal conductivity; a first terminal configured to be formed to correspond to the second portion on a side of the first surface; and a second terminal configured to be formed on a side of the second surface.

First claim

What is claimed is:

1. An electronic component comprising:
a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface;
a first wiring layer provided on the first surface;
a second wiring layer provided on the second surface;
a second portion configured to be formed inside the first wiring layer, and have second thermal conductivity lower than the first thermal conductivity;
a first terminal configured to be formed to correspond to the second portion on a side of the first surface;
a second terminal configured to be formed on a side of the second surface; and
a vias provided side by side with the second portion in a horizontal direction and configured to penetrate the substrate between the first surface and the second surface and couple a first conductor portion in the first wiring layer and a second conductor portion in the second wiring layer.

2. The electronic component according to claim 1 , wherein the second portion includes a hollow portion.

3. The electronic component according to claim 1 , wherein the first wiring layer includes a first insulation layer in which the second portion is provided.

4. The electronic component according to claim 1 , wherein the first terminal includes a solder.

5. An electronic apparatus comprising:
a first electronic component configured to include:
a first substrate configured to include a first portion having first thermal conductivity, and have a first surface and a second surface opposite to the first surface
a first wiring layer provided on the first surface;
a second wiring layer provided on the second surface;
a second portion configured to be formed inside the first wiring layer, and have second thermal conductivity lower than the first thermal conductivity;
a first terminal configured to be formed to correspond to the second portion on a side of the first surface;
a second terminal configured to be formed on a side of the second surface of the first substrate opposite to the first surface; and
a vias provided side by side with the second portion in a horizontal direction and configured to penetrate the substrate between the first surface and the second surface and couple a first conductor portion in the first wiring layer and a second conductor portion in the second wiring layer; and

a second electronic component configured to include a third terminal coupled to the second terminal.

6. The electronic apparatus according to claim 5 , wherein the second electronic component further includes a second substrate configured to include a third portion having third thermal conductivity, and have a third surface and a fourth surface opposite to the third surface, a fourth portion formed inside the third portion and configured to have fourth thermal conductivity lower than the third thermal conductivity, the third terminal formed to correspond to the fourth portion on a side of the third surface, and a fourth terminal formed on a side of the fourth surface of the second substrate, and wherein the electronic apparatus further comprises: a third electronic component configured to include a fifth terminal coupled to the fourth terminal.

7. The electronic apparatus according to claim 6 , wherein the fourth portion has a different volume from the second portion.

8. The electronic apparatus according to claim 5 , further comprising: a fourth electronic component configured to include a sixth terminal coupled to the first terminal.

9. A method of manufacturing an electronic apparatus, the method comprising:
facing a second terminal of a first electronic component to a third terminal of a second electronic component, the first electronic component configured to include:
a first substrate which includes a first portion which has first thermal conductivity;
a first wiring layer provided on the first surface of the first substrate;
a second wiring layer provided on the second surface of the first substrate;
a second portion which is formed inside the first wiring layer and has second thermal conductivity lower than the first thermal conductivity;
a first terminal which is formed to correspond to the second portion on a side of a first surface of the first substrate;
a second terminal which is formed on a side of a second surface of the first substrate opposite to the first surface; and
a vias provided side by side with the second portion in a horizontal direction and configured to penetrate the substrate between the first surface and the second surface and couple a first conductor portion in the first wiring layer and a second conductor portion in the second wiring layer; and

coupling the third terminal and the second terminal by executing heating from a side of the second electronic component.

10. The method of manufacturing the electronic apparatus according to claim 9 , wherein the second electronic component further includes a second substrate configured to include a third portion which has third thermal conductivity, a fourth portion configured to be formed inside the third portion and have fourth thermal conductivity lower than the third thermal conductivity, the third terminal configured to be formed to correspond to the fourth portion on a side of a third surface of the second substrate, and a fourth terminal configured to be formed on a side of a fourth surface of the second substrate opposite to the third surface, and wherein the method further comprises:
after the coupling of the third terminal and the second terminal, facing the fourth terminal of the second electronic component to a fifth terminal of a third electronic component; and
coupling the fourth terminal and the fifth terminal by executing heating from a side of the third electronic component.

11. The method of manufacturing the electronic apparatus according to claim 10 , wherein the fourth portion has a smaller volume than the second portion.

12. The method of manufacturing the electronic apparatus according to claim 9 , wherein before the coupling of the second terminal and the third terminal, a sixth terminal of a fourth electronic component is bonded to the first terminal of the first electronic component.

13. The method of manufacturing the electronic apparatus according to claim 9 , further comprising:
coupling the first terminal to a sixth terminal of a fourth electronic component after the coupling of the second terminal and the third terminal.

14. The electronic component according to claim 1 , wherein a cross-sectional area of the second portion is larger than a cross-sectional area of the first terminal.

15. The electronic component according to claim 1 , wherein the second portion includes bubbles.

16. The electronic apparatus according to claim 5 , wherein a cross-sectional area of the second portion is larger than a cross-sectional area of the first terminal.

17. The electronic apparatus according to claim 5 , wherein the second portion includes bubbles.

18. The method according to claim 9 , wherein a cross-sectional area of the second portion is larger than a cross-sectional area of the first terminal.

19. The method according to claim 9 , wherein the second portion includes bubbles.

Assignees

• Fujitsu Ltd

Inventors

• Kikuchi Ryo
• Imaizumi Nobuhiro
• Onuki Hiroshi

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title