Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9853005-B2
Application number	US-201514792461-A
Country	US
Kind code	B2
Filing date	Jul 6, 2015
Priority date	Jul 9, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first insulating film formed over the semiconductor substrate;
a pad formed over the first insulating film;
a second insulating film formed over the first insulating film so as to cover the pad; and
an opening formed in the second insulating film to expose a part of the pad,
wherein the pad comprises a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component, and
wherein, over the Al-containing conductive film in a region overlapping the opening in a plan view, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is formed,

wherein the second conductor film is in an uppermost layer of the first laminated film,
wherein the copper wire is bonded to the second conductor film,
wherein the first conductor film is a single-layer film or a laminated film including one or more layers of films selected from a group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film,
wherein the second conductor film comprises a palladium film, and
wherein a height from an upper surface of the Al-containing conductive film to an upper surface of the second conductor film in the opening is less than a height from the upper surface of the Al-containing conductive film to an upper surface of the second insulating film formed over the Al-containing conductive film.

2. The semiconductor device according to claim 1 , wherein the first conductor film includes a titanium film and, over the titanium film, the second conductor film is formed.

3. The semiconductor device according to claim 1 , wherein the first conductor film comprises a titanium film.

4. The semiconductor device according to claim 1 , wherein the second conductor film is formed by a sputtering method.

5. The semiconductor device according to claim 1 , wherein, over a portion of the Al-containing conductive film which is covered with the second insulating film, the laminated film including the first conductor film, and the second conductor film over the first conductor film is not formed.

6. The semiconductor device according to claim 1 , wherein the laminated film including the first conductor film, and the second conductor film over the first conductor film is formed over an entire upper surface of the Al-containing conductive film included in the pad.

Assignees

• Renesas Electronics Corp

Inventors

• Maeda Takehiko
• Yajima Akira
• Itou Satoshi
• Kawashiro Fumiyoshi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title