Warpage reduction in structures with electrical circuitry

US9853000B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9853000-B2
Application numberUS-201615181861-A
CountryUS
Kind codeB2
Filing dateJun 14, 2016
Priority dateDec 3, 2013
Publication dateDec 26, 2017
Grant dateDec 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

To reduce warpage in at least one area of a wafer, a stress/warpage management layer ( 810 ) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

First claim

Opening claim text (preview).

The invention claimed is: 1. A structure comprising: an integrated circuit; and a first layer covering a first area of the integrated circuit and not being part of any circuitry, the first layer being bonded to the entire first area except at one or more selected locations within the first area, the first layer reducing a warpage of the integrated circuit in the first area and being sufficient to over-balance the warpage of the first area if bonded to the entire first area. 2. The structure of claim 1 wherein the first layer over-balances the warpage of the first area. 3. The structure of claim 1 wherein at any location at which the first layer is bonded to the first area, the first layer is debondable from the first area by electromagnetic radiation without debonding the first layer from the first area at any other location at which the first layer is bonded to the first area. 4. The structure of claim 1 wherein at any location at which the first layer is bonded to the first area, the first layer is debondable from the first area by heat without debonding the first layer from the first area at any other location at which the first layer is bonded to the first area. 5. The structure of claim 1 wherein the first layer comprises a first sub-layer and a second sub-layer; wherein at each location at which the first layer is bonded to the first area, the second sub-layer comprises an adhesive bonding the first layer to the first area and having a different composition than the first sub-layer; and at each location at which the first layer is not bonded to the first area, the second sub-layer comprises a composition obtainable from the adhesive by application of electromagnetic radiation. 6. The structure of claim 5 wherein the first layer is present in the final structure. 7. The structure of claim 1 wherein the first layer comprises a first sub-layer and a second sub-layer; wherein at each location at which the first layer is bonded to the first area, the second sub-layer comprises an adhesive bonding the first layer to the first area and having a different composition than the first sub-layer; and at each location at which the first layer is not bonded to the first area, the second sub-layer comprises a composition obtainable from the adhesive by application of heat. 8. The structure of claim 1 wherein: at each location at which the first layer is bonded to the first area, the first layer comprises an adhesive bonded to the first area, the adhesive being debondable by application of electromagnetic radiation; and at each location at which the first layer is not bonded to the first area, the first layer comprises a composition obtainable from the adhesive by application of electromagnetic radiation. 9. The structure of claim 1 wherein: at each location at which the first layer is bonded to the first area, the first layer comprises an adhesive bonded to the first area, the adhesive being debondable by application of heat; and at each location at which the first layer is not bonded to the first area, the first layer comprises a composition obtainable from the adhesive by application of heat. 10. The structure of claim 1 wherein the first area is an entire area of the integrated circuit. 11. The structure of claim 1 wherein the first layer is present in the final structure. 12. An assembly comprising: an integrated circuit comprising one or more contact pads on a first side of the integrated circuit; circuitry connected to the one or more contact pads of the integrated circuit; and a first layer covering a first area on a second side of the integrated circuit, the first layer not being part of any circuitry, the first layer being bonded to the entire first area except at one or more selected locations within the first area, the first layer reducing a warpage of the first area. 13. The structure of claim 12 wherein at any location at which the first layer is bonded to the first area, the first layer is debondable from the first area by electromagnetic radiation without debonding the first layer from the first area at any other location at which the first layer is bonded to the first area. 14. The structure of claim 12 wherein at any location at which the first layer is bonded to the first area, the first layer is debondable from the first area by heat without debonding the first layer from the first area at any other location at which the first layer is bonded to the first area. 15. The structure of claim 12 wherein the first layer comprises a first sub-layer and a second sub-layer; wherein at each location at which the first layer is bonded to the first area, the second sub-layer comprises an adhesive bonding the first layer to the first area and having a different composition than the first sub-layer; and at each location at which the first layer is not bonded to the first area, the second sub-layer comprises a composition obtainable from the adhesive by application of electromagnetic radiation. 16. The structure of claim 12 wherein the first layer comprises a first sub-layer and a second sub-layer; wherein at each location at which the first layer is bonded to the first area, the second sub-layer comprises an adhesive bonding the first layer to the first area and having a different composition than the first sub-layer; and at each location at which the first layer is not bonded to the first area, the second sub-layer comprises a composition obtainable from the adhesive by application of heat. 17. The structure of claim 12 wherein: at each location at which the first layer is bonded to the first area, the first layer comprises an adhesive bonded to the first area, the adhesive being debondable by application of electromagnetic radiation; and at each location at which the first layer is not bonded to the first area, the first layer comprises a composition obtainable from the adhesive by application of electromagnetic radiation. 18. The structure of claim 12 wherein: at each location at which the first layer is bonded to the first area, the first layer comprises an adhesive bonded to the first area, the adhesive being debondable by application of heat; and at each location at which the first layer is not bonded to the first area, the first layer comprises a composition obtainable from the adhesive by application of heat. 19. The structure of claim 12 wherein the first area is an entire area of the integrated circuit. 20. The structure of claim 12 wherein the first layer is present in the final structure.

Assignees

Inventors

Classifications

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • Cutting or separating of wafers, substrates or parts of devices · CPC title

  • Deposition of metallic or metal-silicide materials · CPC title

  • in gaseous form, e.g. by CVD or PVD · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

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Frequently asked questions

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What does patent US9853000B2 cover?
To reduce warpage in at least one area of a wafer, a stress/warpage management layer ( 810 ) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-b…
Who is the assignee on this patent?
Invensas Corp
What technology area does this patent fall under?
Primary CPC classification H10W42/121. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).