Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips

Patent metadata

Field	Value
Publication number	US-9852979-B2
Application number	US-201615339550-A
Country	US
Kind code	B2
Filing date	Oct 31, 2016
Priority date	Mar 25, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An electronic system comprising an electronic body ( 301 ) with terminal pads ( 310 ) and at least one capacitor embedded in the electronic body. The capacitor including an insulating and adhesive first polymeric film ( 302 ) covering the body surface except the terminal pads; a sheet ( 320 ) of high-density capacitive elements, the first capacitor terminal being a metal foil ( 321 ) attached to film ( 302 ), the second terminal a conductive polymeric compound ( 324 ), and the insulator a dielectric skin ( 323 ). Sheet ( 320 ) has sets of via holes: the first set holes reaching metal foil 321 ), the second set holes reaching the terminals ( 310 ), and the third set holes reaching the conductive polymeric compound ( 324 ). An insulating second polymeric film ( 303 ) lining the sidewalls of the holes and planarizing the sheet surface; and metal ( 432 ) filling the via holes between the polymeric sidewalls and forming conductive traces and attachment pads on the system surface.

First claim

We claim:

1. A method for fabricating an electronic system comprising:
providing a semiconductor wafer having embedded electronic bodies, the wafer surface having conductive contact pads of the electronic bodies;
laminating an insulating first polymeric film across the wafer surface;
providing a sheet of capacitive elements, one sheet side formed as a metal foil in touch with metal particles, surfaces of the metal particles covered with a dielectric skin, and the opposite sheet side formed by a conductive polymeric material between the metal particles, the sheet operable as a capacitor having the metal as first terminal, the conductive polymer as second terminal, and the dielectric skin of the metal particles as insulator;
attaching the sheet by its metal foil onto the first polymeric film;
opening sets of via-holes of a first diameter into the sheet, the first set holes reaching the metal foil, and the second set holes reaching the wafer contact pads;
laminating an insulating second polymeric film across the wafer, filling the via-holes of the first diameter and planarizing the sheet surface;
opening sets of through-polymer vias of a second diameter into the second polymeric film, the second diameter being smaller than the first diameter, the third set holes, nested inside the first set holes, reaching the metal foil, the fourth set holes, nested inside the second set holes, reaching a contact pad, and a fifth set holes reaching the conductive polymeric surface;
depositing a metal seed layer onto sidewalls and bottoms of the through-polymer vias and the surface of the second polymeric film, creating redistribution traces and attachment pads on the surface; and
plating metal onto the patterned seed layer to fill the through-polymer vias.

2. The method of claim 1 further including the process of concurrently curing the first and second polymeric materials.

3. The method of claim 1 further including the process of singulating the wafer into discrete units, each unit including a system of one or more active semiconductor chips embedded with one or more capacitors composed of high density capacitive elements, and a plurality of attachment pads for external components.

4. The method of claim 1 , wherein the electronic bodies are selected from a group including power supply systems having a DC/DC converter including a synchronous Buck converter, flyback converters, DC/DC boost converters, isolated converters, charge pumps, fuel gauges, power stages with drivers and load switches, voltage references, current references, and current sensors.

5. The method of claim 1 , wherein the dielectric skin is coherent and free of voids.

6. The method of claim 5 , wherein the dielectric skin is an insulating metal oxide layer.

7. The method of claim 3 , wherein the external components include an inductor.

8. The method of claim 1 , wherein the metal foil is suitable to oxidize uniformly and adhere to polymeric compounds.

9. The method of claim 1 wherein, the sets of via holes has a cylindrical shape.

10. The method of claim 1 wherein, the sets of via holes has a conical shape.

11. The method of claim 1 wherein, the capacitor has a thickness of at least 50 μm.

12. The method of claim 2 , wherein the metal particles have a capacitive density of approximately equal to or less than 200 μF/cm 2 .

13. The method of claim 2 , wherein the metal particles have a capacitor stability of up to 125° C.

Assignees

• Texas Instruments Inc

Inventors

• Romig Matthew D
• Stepniak Frank
• Gandhi Saumya

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P14/46

  using a liquid · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title