Area-efficient memory mapping techniques for programmable logic devices

Patent metadata

Field	Value
Publication number	US-9852247-B2
Application number	US-201514713991-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Various techniques are provided to implement a logical memory in programmable logic devices (PLDs) having embedded block RAMs (EBRs). For example, a computer-implemented method includes determining a main area of a logical memory that can be fully mapped to a first one or more EBRs configured in a first depth-width configuration, mapping the main area to the first one or more EBRs, and mapping the remainder of the logical memory to a second one or more EBRs configured in a second or more depth-width configurations. The mapping of the remainder of the logical memory may be performed hierarchically by a recursive process, in some embodiments. The depth-width configurations and the corresponding mapping may be selected according to an efficiency metric, for example. Other embodiments include a system comprising a PLD and a configuration memory storing configuration data generated by such a method, and a PLD configured with such configuration data.

First claim

We claim:

1. A computer-implemented method comprising:
determining, by one or more processors, a main area of a logical memory in a design for a programmable logic device (PLD), the main area being a portion of the logical memory that can be fully mapped to a first set of embedded block RAMs (EBRs) configured in a first depth-width configuration;
mapping the main area to the first set of EBRs;
mapping a subarea of the logical memory to a second set of EBRs configured in one or more depth-width configurations different from the first depth-width configuration, the subarea being a remainder of the logical memory excluding the main area; and
storing configuration data for the PLD, the configuration data identifying the main area mapped to the first set of EBRs and the subarea mapped to the second set of EBRs.

2. The computer-implemented method of claim 1 , further comprising selecting the first depth-width configuration based on a memory area efficiency metric comprising an aggregate size of the first set of EBRs to be mapped to the main area and the second set of EBRs to be mapped to the subarea to implement the logical memory.

3. The computer-implemented method of claim 2 , wherein the memory area efficiency metric further comprises a size of one or more address decoders and/or one or more output multiplexers for implementing the logical memory with the first and second sets of EBRs.

4. The computer-implemented method of claim 2 , wherein the determining of the main area is responsive to the selecting of the first depth-width configuration.

5. The computer-implemented method of claim 1 , wherein the mapping of the subarea of the logical memory comprises:
determining a dependent main area of the subarea, the dependent main area being a portion of the subarea that can be fully mapped to those of the second set of EBRs that are configured in a second depth-width configuration;
mapping the dependent main area to those of the second set of EBRs that are configured in the second depth-width configuration; and
mapping a dependent subarea of the subarea to those of the second set of EBRs that are configured in one or more depth-width configurations different from the first and second depth-width configurations, the dependent subarea being a remainder of the subarea excluding the dependent main area.

6. The computer-implemented method of claim 5 , further comprising selecting the second depth-width configuration based on a memory area efficiency metric comprising an aggregate size of the second set of EBRs to be mapped to implement the subarea of the logical memory.

7. The computer-implemented method of claim 1 , wherein the method is performed recursively with the subarea taking the place of the logical memory at each level of recursion.

8. The computer-implemented method of claim 1 , wherein:
the subarea comprises an L-shaped subarea; and
the mapping of the subarea comprises determining a first division of the L-shaped subarea into a full horizontal subarea and a partial vertical subarea and/or a second division of the L-shaped subarea into a partial horizontal subarea and a full vertical subarea.

9. The computer-implemented method of claim 8 , wherein the mapping of the subarea comprises determining the first division and the second division, and wherein the mapping of the subarea further comprises:
selecting between the first division and the second division based on a memory area efficiency metric comprising an aggregate size of the second set of EBRs to be mapped to implement the subarea of the logical memory; and
mapping the subarea according to the selected one of the first division or second division.

10. The computer-implemented method of claim 1 , further comprising:
determining that a number of the first set of EBRs and the second set of EBRs mapped to implement the logical memory is excessive according to a PLD resource utilization metric; and
replacing a selected one EBR of the first set of EBRs or second set of EBRs with a programmable logic block (PLB) configured as a memory.

11. The computer-implemented method of claim 10 , wherein the determining that the number of the first set of EBRs and second set of EBRs mapped to implement the logical memory is excessive comprises comparing the number of the first set of EBRs and second set of EBRs mapped to implement the logical memory against a number of EBRs available in the PLD.

12. A non-transitory machine-readable medium storing a plurality of machine-readable instructions which, when executed by one or more processors of a computer system, are adapted to cause the computer system to perform the method of claim 1 .

13. A system comprising:
a programmable logic device (PLD) comprising a plurality of embedded block RAMs (EBRs) each configurable in one of a plurality of depth-width configurations;
a configuration memory storing configuration data for the PLD to implement a design that includes a logical memory;
wherein the configuration data configures a first subset of the EBRs in a first depth-width configuration and fully maps a first portion of the logical memory to the first subset of the EBRs; and
wherein the configuration data configures a second subset of the EBRs in one or more depth-width configurations different from the first depth-width configuration and maps a second portion of the logical memory to the second subset of the EBRs.

14. The system of claim 13 , wherein the configuration memory comprises a non-volatile memory embedded in the PLD.

15. The system of claim 13 , wherein the configuration memory comprises a non-volatile memory communicatively coupled to the PLD.

16. The system of claim 13 , wherein the second portion of the logical memory is a remainder of the logical memory excluding the first portion.

17. The system of claim 13 , wherein:
the PLD further comprises a plurality of programmable logic blocks (PLBs) comprising look-up tables (LUTs) and configurable to provide logic functionalities or distributed memory functionalities; and
the configuration data configures one or more of the PLBs as distributed memories and maps a third portion of the logical memory to the one or more of the PLBs.

18. The system of claim 13 , wherein:
the PLD further comprises a plurality of programmable logic blocks (PLBs) comprising look-up tables (LUTs) and configurable to provide logic functionalities; and
the configuration data configures one or more of the PLBs to operate as an address decoder and/or an output multiplexer to implement the logical memory with the first and second subsets of the EBRs.

19. The system of claim 13 , wherein the respective depth-width configurations for the first and second subsets of the EBRs are selected based on a memory area efficiency metric comprising an aggregate size of the first and second subsets of the EBRs mapped to implement the logical memory.

20. A programmable logic device (PLD) configured with a design including a logical memory, the PLD comprising:
a plurality of embedded block RAMs (EBRs) configurable according to a plurality of depth-width configurations;
wherein a first subset of the EBRs is configured in a first depth-width configuration and fully mapped by a portion of the logical memory; and
wherein a second subset of the EBRs is configured in one or more depth-width configurations different from the first depth-width configuration and mapped by a remainder of the logical memory excluding the portion mapped to the first subset of the EBRs.

Assignees

• Lattice Semiconductor Corp

Inventors

• Yao Peng
• Rajappan Venkat
• Hegade Sreepada

Classifications

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F17/5054 Primary

  Physics · mapped topic

• G06F17/5045

  Physics · mapped topic

• G06F30/347 Primary

  Physical level, e.g. placement or routing · CPC title