Power-aware RAM processing

Patent metadata

Field	Value
Publication number	US-9330733-B1
Application number	US-201113012717-A
Country	US
Kind code	B1
Filing date	Jan 24, 2011
Priority date	Sep 20, 2005
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

First claim

What is claimed is:

1. A method for memory access in a programmable logic device, the method comprising:
receiving a logical memory block configuration layout;
identifying, based on the logical memory block configuration layout, at least two potential mappings of a plurality of embedded memory blocks from the programmable logic device, wherein:
the plurality of embedded memory blocks is coupled to a plurality of memory ports, and
the plurality of memory ports is enabled by a common clock signal;

selecting one of the at least two potential mappings based on power consumption of each potential mapping, wherein the power consumption of each potential mapping is determined based on determining a number of embedded memory blocks, a number of ports in the plurality of memory ports that are associated with the potential mapping, and a size of associated logic circuits, and the power consumption of the selected potential mapping is less than the power consumption of at least one unselected potential mapping;
implementing the logical memory block configuration layout using the selected potential mapping; and
disabling a first memory port from the plurality of memory ports in response to a determination that the first memory port is unused in the implementation.

2. The method of claim 1 , wherein the identifying is performed in response to a total power consumption of the plurality of embedded memory blocks.

3. The method of claim 1 , wherein the disabling of the first memory port further comprises disabling a bit line precharge unit coupled to the first memory port.

4. The method of claim 1 , wherein the disabling of the first memory port further comprises disabling a sense amplifier coupled to the first memory port.

5. The method of claim 1 , wherein the logical memory block configuration layout comprises a logical memory bit width and a logical memory bit depth.

6. The method of claim 1 , further comprising:
selectively enabling a second memory port from the plurality of memory ports in response to a determination that the second memory port is selectively used in the implementation.

7. The method of claim 6 , wherein selectively enabling the second memory port comprises:
setting a read enable input to a logical-high value, wherein the read enable input is coupled to a latch; and
generating a modified read clock enable signal as an output of a logical-AND operation between a read clock enable signal and a read enable signal.

8. The method of claim 1 , wherein the disabling of the first memory port comprises:
generating a modified clock signal as an output of a logical AND operation between a logical low signal and the common clock signal; and
clocking the first memory port using the modified clock signal to selectively deactivate a bitline precharge unit connected to a first embedded memory block in the plurality of embedded memory blocks.

9. An integrated circuit, the integrated circuit comprising:
configuration circuitry, the configuration circuitry operable to:
receive a logical memory block configuration layout;
identify, based on the logical memory block configuration layout, at least two potential mappings of a plurality of embedded memory blocks from the integrated circuit, wherein:
the plurality of embedded memory blocks coupled to a plurality of memory ports, and
the plurality of memory ports is enabled by a common clock signal; and

select one of the at least two potential mappings based on power consumption of each potential mapping, wherein the power consumption of each potential mapping is determined based on determining a number of embedded memory blocks, a number of ports in the plurality of memory ports that are associated with the potential mapping, and an amount of associated logic circuits, and the power consumption of the selected potential mapping is less than the power consumption of at least one unselected potential mapping;
implement the logical memory block configuration layout using the selected potential mapping; and

power control circuitry, the power control circuitry operable to disable a first memory port from the plurality of memory ports.

10. The integrated circuit of claim 9 , wherein the configuration circuitry is further configured to perform the identifying in response to a total power consumption of the plurality of embedded memory blocks.

11. The integrated circuit of claim 9 , wherein the power control circuitry is further configured to disable the first memory port by disabling a bit line precharge unit coupled to the first memory port.

12. The integrated circuit of claim 9 , wherein the power control circuitry is further configured to disable the first memory port by disabling a sense amplifier coupled to the first memory port.

13. The integrated circuit of claim 9 , wherein the configuration circuitry is further configured to perform the identifying in response to one or more timing estimates associated with the plurality of embedded memory blocks.

14. The integrated circuit of claim 9 , wherein the power control circuitry is further operable to selectively enable a second memory port from the plurality of memory ports in response to a determination that the second memory port is selectively used in the implementation.

15. The integrated circuit of claim 14 , wherein the power control circuitry is further configured to selectively enable the second memory port by:
setting a read enable input to a logical-high value, wherein the read enable input is coupled to a latch; and
generating a modified read clock enable signal as an output of a logical-AND operation between a read clock enable signal and a read enable signal.

16. The integrated circuit of claim 9 , wherein the power control circuitry is operable to disable the first memory port by:
generating a modified clock signal as an output of a logical AND operation between a logical low signal and the common clock signal; and
clocking the first memory port using the modified clock signal to selectively deactivate a bitline precharge unit connected to a first embedded memory block in the plurality of embedded memory blocks.

17. An integrated circuit, the integrated circuit comprising:
configuration circuitry, the configuration circuitry operable to:
receive a logical memory block configuration layout;
identify at least two potential mappings of a plurality of embedded memory blocks from the integrated circuit, the plurality of embedded memory blocks coupled to a plurality of memory ports, based on the received logical memory block configuration layout associated with the plurality of embedded memory blocks; and
select one of the at least two potential mappings based on power consumption of each potential mapping, wherein the power consumption of each potential mapping is determined based on determining a number of embedded memory blocks, a number of ports in the plurality of memory ports that are associated with the potential mapping, and an amount of associated logic circuits, and the power consumption of the selected potential mapping is less than the power consumption of at least one unselected potential mapping;
implement the logical memory block configuration layout using the selected potential mapping; and

power control circuitry, the power control circuitry operable to selectively enable a memory port from the plurality of memory ports.

18. The integrated circuit of claim 17 , wherein the configuration circuitry is further configured to perform the identifying in response to a total power consumption of the plurality of embedded

Assignees

• Tessier Russell George
• Betz Vaughn Timothy
• Golpalsamy Thiagaraja
• Neto David
• Altera Corp

Inventors

• Tessier Russell George
• Betz Vaughn Timothy
• Golpalsamy Thiagaraja
• Neto David

Classifications

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C2207/2227

  Standby or low power modes · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title